Muutke küpsiste eelistusi

E-raamat: Birthing the Computer: From Relays to Vacuum Tubes

Teised raamatud teemal:
  • Formaat - PDF+DRM
  • Hind: 129,99 €*
  • * hind on lõplik, st. muud allahindlused enam ei rakendu
  • Lisa ostukorvi
  • Lisa soovinimekirja
  • See e-raamat on mõeldud ainult isiklikuks kasutamiseks. E-raamatuid ei saa tagastada.
Birthing the Computer: From Relays to Vacuum TubesSuurem pilt
Teised raamatud teemal:

DRM piirangud

  • Kopeerimine (copy/paste):

    ei ole lubatud

  • Printimine:

    ei ole lubatud

  • Kasutamine:

    Digitaalõiguste kaitse (DRM)
    Kirjastus on väljastanud selle e-raamatu krüpteeritud kujul, mis tähendab, et selle lugemiseks peate installeerima spetsiaalse tarkvara. Samuti peate looma endale  Adobe ID Rohkem infot siin. E-raamatut saab lugeda 1 kasutaja ning alla laadida kuni 6'de seadmesse (kõik autoriseeritud sama Adobe ID-ga).

    Vajalik tarkvara
    Mobiilsetes seadmetes (telefon või tahvelarvuti) lugemiseks peate installeerima selle tasuta rakenduse: PocketBook Reader (iOS / Android)

    PC või Mac seadmes lugemiseks peate installima Adobe Digital Editionsi (Seeon tasuta rakendus spetsiaalselt e-raamatute lugemiseks. Seda ei tohi segamini ajada Adober Reader'iga, mis tõenäoliselt on juba teie arvutisse installeeritud )

    Seda e-raamatut ei saa lugeda Amazon Kindle's. 

Birthing the Computer: From Relays to Vacuum Tubes is the first in a multi-volume series on historical computing machines. This series will span the development of computer systems from the Zuse machines of the early 1930s to about 1995 when microprocessors began to be commoditized. Each volume will focus on a range of technologies, or a class of machines or a particular vendor, and will describe the hardware of the machines and its peripherals, the operating system and system software, and its influence upon programming languages. This volume begins with the Zuse machines which were constructed from relays, but contained the basic elements of a computer system, namely input, computing engine, and output. Early machines from Atanasoff and Berry, Aiken, Stibitz, and IBM are described. The transition from relays to vacuum tubes increased speed and performance significantly, and led to the first true computers in ENIAC, EDSAC, and EDVAC which used paper tape and Williams tubes for I/O and storage. These machines were built by universities.Several early machines were purpose built such as Colossus and BINAC, and created with government support and industrial know-how. By the mid-to-late '50s, computing machines were being built by universities (the SSEM, Whirlwind, and IAS machines), governments (the NBS SEAC and SWAC, and several other machines), and industry (the UNIVAC series and the English Electric DEUCE). Most of these machines were constructed using the von Neumann architecture, and represent an evolution of thinking in how computing machines were to operate along with some innovative ideas in software and programming languages. By the end of the 1950s, the design, development, programming and use of computing machines were in full ferment as many new ideas were proposed, many different machines were designed and some were constructed. Computing machines became a commercial enterprise. Governments receded from building machines to levying requirements and funding construction, while universities continued to explore new architectures, new operating systems, and new programming languages.
List of Figures
xv
List of Tables
xix
Part I Precursor Machines
1(78)
Chapter One Konrad Zuse's Computers
3(21)
1.1 The Z1
5(1)
1.2 The Z2
6(1)
1.3 The Z3
7(6)
1.3.1 Z3 Architecture
9(1)
1.3.2 Memory
10(1)
1.3.3 Floating Point Registers
10(1)
1.3.4 Input and Output
10(1)
1.3.5 Instruction Execution
11(1)
1.3.6 Instruction Set
11(1)
1.3.7 Programming the Z3
12(1)
1.3.8 Z3 Assessment
12(1)
1.4 The Z4
13(3)
1.4.1 ETH and the Z4
14(1)
1.4.2 The Z5
15(1)
1.5 Plankalkul
16(1)
1.6 The Z11
17(2)
1.7 The Z22
19(1)
1.8 The Z23
20(1)
1.9 The Z31
21(1)
1.10 Assessment of Zuse's Computing Machines
22(2)
Chapter Two The Atanasoff-Berry Computer
24(6)
2.1 ABC System Architecture
24(3)
2.2 The Atanasoff-Mauchly Conflict
27(1)
2.3 The ABC Reconstructed
28(1)
2.4 ABC Assessment
28(2)
Chapter Three Stibitz's Relay Computers
30(9)
3.1 Model I: The Complex Numerical Calculator
32(1)
3.2 Model II: The Relay Interpolator
33(1)
3.3 Model III: The Ballistic Computer
34(1)
3.4 Model IV: The Error Detector Mark II
35(1)
3.5 Model V
35(1)
3.6 Model VI
36(1)
3.7 Later BTL Machines
37(1)
3.8 Assessment of Stibitz's Relay Computers
37(2)
Chapter Four Colossus
39(12)
4.1 Rebuilding Colossus
44(2)
4.2 Colossus Architecture
46(1)
4.3 Colossus and Code Breaking
47(2)
4.4 Assessment of Colossus
49(2)
Chapter Five Aiken's ASCC/Mark I
51(8)
5.1 ASCC System Architecture
54(2)
5.1.1 Automatic Sequence Unit
54(1)
5.1.2 Arithmetic Calculations
55(1)
5.1.3 Interpolators
55(1)
5.1.4 Special Registers
56(1)
5.2 I/O System
56(1)
5.3 Programming the ASCC
56(1)
5.4 ASCC Assessment
57(2)
Chapter Six Harvard Mark Machines
59(5)
6.1 Mark II
59(2)
6.2 Mark III
61(2)
6.3 Mark IV
63(1)
6.4 Mark Machines Assessment
63(1)
Chapter Seven IBM's Selective Sequence Electronic Calculator
64(8)
7.1 SSEC System Architecture
66(3)
7.1.1 Electronic Storage Units
67(1)
7.1.2 Relay Storage
67(1)
7.1.3 Tape Storage
67(1)
7.1.4 Dial Storage
67(1)
7.1.5 Pluggable Storage
67(1)
7.1.6 Program Tapes
68(1)
7.2 SSEC Reliability
69(1)
7.3 SSEC Assessment
70(2)
Chapter Eight Who Invented the Computer?
72(7)
Further Reading
73(3)
Exercises for the Reader
76(3)
Part II Pre-Stored Program Machines
79(72)
Chapter Nine ENIAC
80(14)
9.1 ENIAC System Architecture
84(4)
9.1.1 Accumulators
85(1)
9.1.2 Control Units
86(1)
9.1.3 Master Programmer
86(1)
9.1.4 Arithmetic Units
86(1)
9.1.5 Constant Transmitter
87(1)
9.1.6 Function Table
87(1)
9.1.7 Input/Output Units
87(1)
9.2 Later Modifications
88(1)
9.3 Applying ENIAC
88(1)
9.4 The ENIAC Women
89(1)
9.5 Myths and Stories About ENIAC
90(1)
9.6 Assessment of ENIAC
91(3)
Chapter Ten EDVAC
94(17)
10.1 The Von Neumann Report
95(2)
10.2 The Patent Dispute
97(1)
10.3 The "Real" EDVAC
97(2)
10.4 EDVAC Architecture
99(4)
10.4.1 System Architecture
99(1)
10.4.2 Memory System
100(1)
10.4.3 I/O System
101(1)
10.4.4 The EDVAC Console
101(2)
10.4.5 Debugging Support
103(1)
10.5 EDVAC Instruction Set
103(2)
10.6 Physical Challenges
105(2)
10.7 EDVAC Implementation
107(1)
10.8 EDVAC Software
108(1)
10.9 EDVAC Applications
109(1)
10.9.1 EDVAC Operation
110(1)
10.10 EDVAC Assessment
110(1)
Chapter Eleven EDSAC
111(12)
11.1 EDSAC System Architecture
112(3)
11.2 The EDSAC Order Code
115(1)
11.3 Programming the EDSAC
116(4)
11.3.1 Subroutine Libraries
117(2)
11.3.2 The Travails of Paper Tape
119(1)
11.3.3 An EDSAC Simulator
119(1)
11.4 EDSAC Firsts
120(1)
11.5 EDSAC 2
120(2)
11.6 EDSAC Assessment
122(1)
Chapter Twelve Manchester SSEM
123(7)
12.1 The SSEM Architecture
127(2)
12.2 Assessment of the SSEM
129(1)
Chapter Thirteen BINAC
130(4)
13.1 System Architecture
131(1)
13.2 Instruction Set
131(1)
13.3 BINAC Assessment
132(2)
Chapter Fourteen Pilot ACE
134(6)
14.1 Pilot A CE System Architecture
136(1)
14.2 Programming the Pilot ACE
137(1)
14.3 Pilot A CE Assessment
138(1)
14.4 The ACE
139(1)
Chapter Fifteen BRLESC
140(11)
15.1 BRLESC I
140(3)
15.2 BRLESC II
143(1)
15.3 BRLESC Assessment
144(7)
Further Reading
146(3)
Exercises for the Reader
149(2)
Part III Vacuum Tube Machines
151(179)
Chapter Sixteen Engineering Research Associates
154(14)
16.1 ERA 1101 Architecture
158(6)
16.1.1 System Architecture
160(2)
16.1.2 I/O Systems
162(1)
16.1.3 UNIVAC 1101 Instruction Set
162(2)
16.1.4 The Atlas II
164(1)
16.2 UNIVAC 1102
164(2)
16.3 Dissonance at Remington Rand
166(1)
16.4 Assessment of the UNIVAC 1101
166(2)
Chapter Seventeen UNIVAC 1103
168(17)
17.1 UNIVAC 1103 System Architecture
168(3)
17.1.1 Control Components
170(1)
17.1.2 Arithmetic Registers
171(1)
17.1.3 Master Clock
171(1)
17.2 Storage
171(1)
17.3 Arithmetic
172(1)
17.4 Instruction Format
173(7)
17.4.1 Transmissive Instructions
174(1)
17.4.2 Replace Instructions
175(1)
17.4.3 Split Instructions
175(1)
17.4.4 Q-Controlled Instructions
176(1)
17.4.5 Sequenced Instructions
176(2)
17.4.6 One-Way Conditional Jump Instructions
178(1)
17.4.7 Two-Way Conditional Jump Instructions
178(1)
17.4.8 One-Way Unconditional Jump Instructions
179(1)
17.4.9 External Equipment Instructions
179(1)
17.4.10 Stop Instructions
180(1)
17.5 I/O Systems
180(2)
17.5.1 I/O Registers
181(1)
17.5.2 Program Interrupts
181(1)
17.6 UNIVAC 1103 A
182(1)
17.7 UNIVAC 1104
183(1)
17.8 Assessment of the Early UNIVAC I lxx Machines
184(1)
Chapter Eighteen NBS Computing Machines
185(11)
18.1 SEAC
185(3)
18.1.1 SEAC System Architecture
187(1)
18.1.2 Applications
188(1)
18.2 SWAC
188(5)
18.2.1 System Architecture
191(1)
18.2.2 Instruction Set
192(1)
18.2.3 Software
192(1)
18.3 DYSEAC
193(2)
18.4 NBS Computer Assessment
195(1)
Chapter Nineteen MIT Whirlwind
196(10)
19.1 Whirlwind System Architecture
198(3)
19.1.1 Arithmetic Unit
199(1)
19.1.2 Registers
199(1)
19.1.3 Magnetic Core Memory
199(1)
19.1.4 Auxiliary Storage
199(1)
19.1.5 I/O System
200(1)
19.2 Whirlwind Instruction Set
201(2)
19.3 Sample Whirlwind Program
203(2)
19.4 Whirlwind Assessment
205(1)
Chapter Twenty The IAS Machine
206(7)
20.1 IAS System Architecture
208(2)
20.2 IAS Orders
210(1)
20.3 Assessment of the IAS
211(2)
Chapter Twenty-One MANIAC I
213(16)
21.1 MANIAC System Architecture
213(3)
21.2 MANIAC Instruction Set
216(3)
21.3 Programming the MANIAC
219(2)
21.4 MANIAC II
221(3)
21.4.1 MANIAC II System Architecture
222(1)
21.4.2 Demand Paging
223(1)
21.4.3 Peripherals
223(1)
21.5 Chess Playing
224(1)
21.6 MANIAC III
224(3)
21.6.1 MANIAC III System Architecture
225(1)
21.6.2 MANIAC III Instruction Set
226(1)
21.7 MANIAC Assessment
227(2)
Chapter Twenty-Two The ORDVAC Computer
229(12)
22.1 ORDVAC System Architecture
231(3)
22.1.1 Arithmetic and Control Units
232(2)
22.1.2 Memory
234(1)
22.1.3 I/O Devices
234(1)
22.2 Error Checking the ORDVAC
234(1)
22.3 ORDVAC Instruction Set
235(4)
22.4 Assessment of ORDVAC
239(2)
Chapter Twenty-Three UNIVAC I
241(20)
23.1 UNIVAC I at Lawrence Livermore
242(2)
23.2 Early UNIVAC Orders
244(3)
23.3 UNIVAC I at the Census Bureau
247(1)
23.4 UNIVAC I Architecture
247(2)
23.4.1 UNIVAC I Memory
247(1)
23.4.2 UNIVAC II/O
248(1)
23.5 UNIVAC I Instruction Set
249(3)
23.6 UNIVAC I and Programming
252(3)
23.7 Remington Rand's Problems
255(1)
23.8 UNIVAC II
256(1)
23.9 UNIVAC III
257(3)
23.10 UNIVAC I-III Assessment
260(1)
Chapter Twenty-Four English Electric DEUCE
261(15)
24.1 Basic Architecture
263(1)
24.2 Hardware Configuration
264(1)
24.3 The Control
265(1)
24.4 Instruction Highway
265(2)
24.5 Main Memory
267(1)
24.6 The Magnetic Store
268(1)
24.7 I/O Devices
269(1)
24.8 Instruction Set
269(1)
24.9 UTECOM
270(1)
24.10 EASICODE
270(4)
24.11 Assessment of the DEUCE
274(2)
Chapter Twenty-Five Ferranti Pegasus
276(9)
25.1 Pegasus Configuration
278(3)
25.1.1 Control Unit
279(1)
25.1.2 The Main Store
279(1)
25.1.3 The Computing Store
280(1)
25.1.4 Control Panel
281(1)
25.1.5 I/O System
281(1)
25.2 Pegasus Instruction Set
281(1)
25.3 Pegasus I at the British Science Museum
282(2)
25.4 Pegasus Assessment
284(1)
Chapter Twenty-Six Ferranti Mark I/II
285(9)
26.1 Ferranti Mark I
285(2)
26.2 Mark I Architecture
287(1)
26.3 Mark I Instruction Set
288(3)
26.3.1 Arithmetic and Logical Orders
288(1)
26.3.2 B-Line Manipulation Orders
289(1)
26.3.3 Control Transfer Orders
289(1)
26.3.4 Peripheral and Miscellaneous Orders
290(1)
26.4 Programming the Ferranti Mark I
291(1)
26.5 Assessment of the Mark!
292(2)
Chapter Twenty-Seven Ferranti Mercury
294(6)
27.1 System Architecture
296(1)
27.2 Instruction Set
296(1)
27.3 Mercury Autocode
296(2)
27.4 Mercury Installations
298(1)
27.5 Assessment of the Ferranti Machines
299(1)
Chapter Twenty-Eight Univac File Computers
300(17)
28.1 The File 0 Machine
301(3)
28.2 The File 1 /File 2 Machines
304(6)
28.3 Arithmetic and Control Unit
310(1)
28.4 I/O Systems
310(4)
28.4.1 I/O Storage
311(1)
28.4.2 Buffer Storage
312(1)
28.4.3 High-Speed Storage
312(1)
28.4.4 Large Capacity Drum
312(2)
28.5 File Computer Operations
314(2)
28.6 File Computer Assessment
316(1)
Chapter Twenty-Nine IBM 305 RAMAC
317(13)
29.1 RAMAC Origins
318(1)
29.2 IBM 305 System Architecture
319(4)
29.2.1 Processing Unit and Main Memory
320(1)
29.2.2 Input Card Reader
321(1)
29.2.3 Output Printer and Punch
322(1)
29.2.4 System Console
322(1)
29.3 Instruction Format
323(2)
29.3.1 Accumulators
324(1)
29.4 Controlling the IBM 305
325(3)
29.5 IBM 350 Disk File
328(1)
29.6 IBM 305 Assessment
328(2)
Further Reading 330(3)
Exercises for the Reader 333(2)
Glossary 335(2)
References 337(12)
Index 349
Stephen H. Kaisler, DSc, is a Research Scientist based in Columbia, Maryland, USA, and has worked for a number of small businesses in the Washington Metro Area in the areas of defense and intelligence. He has also worked as a Program Manager in Strategic Computing at the Defense Advanced Research Projects Agency and as Technical Advisor to the US Senate Sergeant at Arms. Dr Kaisler has previously written five books on operating systems, database systems, the Interlisp programming language, software paradigms, and big data, and has published over 40 technical papers and numerous technical reports. Dr Kaisler is currently an Adjunct Professor of Engineering in the Department of Computer Science at George Washington University, USA, and has taught enterprise architecture and information security for seven years at the Business School of the same university. He is a Life Member of the IEEE Computer Society, and received a BS in Physics and MS in Computer Science from the University of Maryland, and a DSc in Computer Science from George Washington University.
Lisainfo e-raamatute kohta Lisainfo e-raamatute kohta
Püsilink: https://www.kriso.ee/db/97814438963132e.html
Märksõnad: