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E-raamat: Channel Coding: Theory, Algorithms, and Applications: Academic Press Library in Mobile and Wireless Communications

Editor-in-chief (ETIS ENSEA/univ. Cergy-Pontoise/CNRS UMR-8051), Editor-in-chief (Universitat Pompeu Fabra, Barcelona, Spain.), Editor-in-chief (ETIS ENSEA/univ. Cergy-Pontoise/CNRS UMR-8051)
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  • Ilmumisaeg: 29-Jul-2014
  • Kirjastus: Academic Press Inc
  • Keel: eng
  • ISBN-13: 9780123972231
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  • Kirjastus: Academic Press Inc
  • Keel: eng
  • ISBN-13: 9780123972231
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This book gives a review of the principles, methods and techniques of important and emerging research topics and technologies in Channel Coding, including theory, algorithms, and applications.

Edited by leading people in the field who, through their reputation, have been able to commission experts to write on a particular topic.

With this reference source you will:

  • Quickly grasp a new area of research
  • Understand the underlying principles of a topic and its applications
  • Ascertain how a topic relates to other areas and learn of the research issues yet to be resolved



    • Quick tutorial reviews of important and emerging topics of research in Channel Coding
    • Presents core principles in Channel Coding theory and shows their applications
    • Reference content on core principles, technologies, algorithms and applications
    • Comprehensive references to journal articles and other literature on which to build further, more specific and detailed knowledge

    Muu info

    Quickly grasp and understand new hot topics of research in channel coding from world-wide leading experts
    Preface xv
    Contributors xvii
    Chapter 1 Turbo Codes: From First Principles to Recent Standards
    1(52)
    1 Introduction
    2(1)
    2 History of turbo codes
    2(6)
    2.1 The origins of turbo codes
    3(1)
    2.2 Concatenation
    3(1)
    2.3 Negative feedback in the decoder and recursive systematic convolutional codes
    3(1)
    2.4 Extrinsic information and iterative decoding
    4(2)
    2.5 Parallel concatenation
    6(2)
    3 Fundamentals of turbo coding
    8(18)
    3.1 Recursive systematic convolutional (RSC) component codes
    8(5)
    3.2 Block coding with turbo codes
    13(5)
    3.3 The permutation
    18(8)
    4 Fundamentals of turbo decoding
    26(12)
    4.1 The turbo principle
    26(4)
    4.2 Soft-input soft-output decoding
    30(8)
    5 Industrial impacts of turbo codes
    38(9)
    5.1 The very first implementations of turbo codecs
    38(3)
    5.2 Early applications of turbo codes
    41(2)
    5.3 Turbo codes in standards
    43(4)
    6 Conclusion
    47(6)
    References
    47(6)
    Chapter 2 Turbo-Like Codes Constructions
    53(88)
    1 Introduction and bibliography survey
    55(4)
    1.1 Introduction
    55(4)
    2 Structure of concatenated codes
    59(14)
    2.1 Main characteristics of turbo encoding structures
    59(3)
    2.2 Trellis encoders
    62(1)
    2.3 Mapper
    63(3)
    2.4 Interleaver
    66(1)
    2.5 Rate conversion modules
    67(1)
    2.6 Puncturer
    68(1)
    2.7 Summary of encoding modules
    68(1)
    2.8 Some turbo encoder structures and their main properties
    68(3)
    2.9 Convolutional versus block encoding
    71(2)
    3 ML analysis and design of constituent codes
    73(16)
    3.1 Maximum-likelihood analysis
    74(6)
    3.2 Design criteria for constituent encoders
    80(7)
    3.3 Comparison between parallel and serially concatenated codes
    87(1)
    3.4 Finding the optimum constituent encoders
    88(1)
    4 Iterative decoding
    89(11)
    4.1 Messages in iterative decoders and independence assumption
    90(3)
    4.2 Soft-input soft-output modules
    93(1)
    4.3 The SISO for the data ordering encoding modules
    93(2)
    4.4 The SISO module for the trellis encoder
    95(2)
    4.5 The SISO module for the mapper
    97(2)
    4.6 Multiple code representations
    99(1)
    5 Interleaver designs
    100(21)
    5.1 Interleaver theory
    100(1)
    5.2 Interleaves: basic definitions
    100(6)
    5.3 Connections among interleaver parameters
    106(1)
    5.4 Convolutional and block interleavers
    107(5)
    5.5 Some practical interleavers
    112(9)
    6 Performances
    121(20)
    6.1 Introduction
    121(1)
    6.2 Iterative decoding versus ML upper bounds
    122(1)
    6.3 Optimality of constituent encoders
    123(1)
    6.4 Performance versus number of iterations
    123(3)
    6.5 Comparison between PCCC and SCCC
    126(3)
    6.6 Other concatenated structures
    129(9)
    References
    138(3)
    Chapter 3 Low-Density Parity-Check Code Constructions
    141(70)
    1 Introduction
    142(1)
    2 LDPC codes and ensembles
    143(13)
    2.1 Gallager ensemble
    144(1)
    2.2 Unstructured irregular ensemble
    145(1)
    2.3 Repeat-accumulate code ensemble
    146(2)
    2.4 Multi-edge type ensemble
    148(3)
    2.5 Protograph ensemble
    151(3)
    2.6 LDPC convolutional code ensemble
    154(2)
    3 Asymptotic analysis and optimization
    156(10)
    3.1 Asymptotic threshold
    156(5)
    3.2 Weight distribution
    161(3)
    3.3 Optimization via differential evolution
    164(2)
    4 Finite-length construction
    166(23)
    4.1 Unstructured codes
    167(18)
    4.2 Structured codes
    185(4)
    5 LDPC codes in standards
    189(22)
    5.1 IEEE 802.16-2009 LDPC codes
    189(2)
    5.2 ITU-T G.9960 LDPC codes
    191(2)
    5.3 CCSDS LDPC codes
    193(1)
    5.4 Other standards including LDPC codes
    194(1)
    5.5 Details of parity-check matrices
    195(8)
    Acknowledgments
    203(1)
    References
    203(8)
    Chapter 4 LDPC Decoders
    211(50)
    1 Introduction
    212(6)
    1.1 A decoding-oriented approach to coding
    212(1)
    1.2 Decoding complexity, long codes, and Shannon limit
    213(1)
    1.3 Evolution of LDPC decoding from Gallager to our days
    214(4)
    1.4
    Chapter's organization
    218(1)
    2 Notation and terminology
    218(3)
    3 Binary LDPC decoders
    221(18)
    3.1 Bit-flipping decoding
    221(1)
    3.2 Hard-decision MP decoders
    222(4)
    3.3 Belief-propagation decoding
    226(4)
    3.4 Min-sum decoding
    230(2)
    3.5 Min-sum-based decoding
    232(3)
    3.6 Erasure decoding
    235(3)
    3.7 Further readings
    238(1)
    4 Non-binary LDPC decoders
    239(22)
    4.1 Notation update
    240(1)
    4.2 Belief-propagation decoding
    241(3)
    4.3 Min-sum decoding
    244(2)
    4.4 Extended-min-sum decoding
    246(1)
    4.5 Min-max decoding
    247(2)
    4.6 Erasure decoding
    249(2)
    4.7 Further readings
    251(1)
    Appendix
    252(1)
    References
    252(9)
    Chapter 5 Code Design with EXIT Charts
    261(38)
    1 Introduction
    262(1)
    1.1 System model
    262(1)
    1.2 Notation
    263(1)
    2 Parallel concatenated codes
    263(11)
    2.1 Encoder and decoder
    263(2)
    2.2 The EXIT method
    265(6)
    2.3 Code analysis and design
    271(3)
    3 Serially concatenated codes
    274(6)
    3.1 Encoder and decoder
    275(1)
    3.2 EXIT analysis
    276(3)
    3.3 Code analysis and design
    279(1)
    4 LDPC codes
    280(11)
    4.1 Decoder and decoding models
    281(5)
    4.2 Analysis and design for the BEC
    286(3)
    4.3 Analysis and design for the AWGN channel
    289(2)
    5 Comments and generalizations
    291(3)
    5.1 Estimation of mutual information
    291(1)
    5.2 Theory of EXIT analysis
    292(1)
    5.3 EXIT analysis for other codes or coded systems
    293(1)
    6 Summary
    294(5)
    References
    294(5)
    Chapter 6 Failures and Error Floors of Iterative Decoders
    299(44)
    1 Introduction
    300(6)
    2 Preliminaries
    306(3)
    2.1 LDPC codes
    306(1)
    2.2 Channel assumptions
    306(1)
    2.3 Message passing decoding algorithms
    307(1)
    2.4 Bit flipping algorithms
    308(1)
    3 Overview of decoding failures
    309(4)
    4 Combinatorial characterization of decoding failures
    313(2)
    4.1 Trapping sets on the BEC
    313(1)
    4.2 Trapping sets on the BSC
    313(2)
    4.3 Trapping sets on the AWGNC
    315(1)
    5 Case study: Column-weight-three codes with the Gallager A/B algorithm on the BSC
    315(6)
    5.1 Graphical representation
    315(1)
    5.2 Topological relation
    316(1)
    5.3 Evolution of trapping sets
    317(1)
    5.4 FER estimation
    318(3)
    6 Combating error floors
    321(10)
    6.1 Improving error floor performance by constructing better Tanner graphs
    321(6)
    6.2 Improving error floor performance by designing better decoders
    327(4)
    7 Connections to LP decoding
    331(3)
    7.1 Pseudo-codewords for LP decoders
    332(2)
    8 Conclusion
    334(9)
    Acknowledgments
    335(1)
    References
    335(8)
    Chapter 7 Rate-Compatible LDPC and Turbo Codes for Link Adaptivity and Unequal Error Protection
    343(26)
    1 Unequal error protection Turbo codes
    344(11)
    1.1 Puncturing and pruning
    344(3)
    1.2 Hybrid Turbo codes and their convergence
    347(4)
    1.3 Interleaver structures
    351(4)
    2 Unequal error protection LDPC codes based on puncturing and pruning
    355(6)
    2.1 Density evolution for general RC-LDPC codes
    356(1)
    2.2 Design of good puncturing patterns for a given mother code
    357(1)
    2.3 Pruning for creating irregular UEP check-node profiles
    358(1)
    2.4 Structured RC-LDPC codes
    359(2)
    3 Unequal error protection LDPC codes based on degree distribution optimization '
    361(8)
    3.1 Multi-edge-type UEP LDPC codes
    362(1)
    References
    363(6)
    Chapter 8 Rateless Coding
    369(30)
    1 Introduction
    370(1)
    2 The fountain paradigm
    370(3)
    2.1 Fountain coding and decoding: definitions and principles
    370(1)
    2.2 The random binary fountain code
    371(2)
    3 Rateless sparse-graph codes for the binary erasure channel: LT and Raptor codes
    373(5)
    3.1 LT codes
    373(2)
    3.2 Raptor codes
    375(2)
    3.3 Decoding algorithms for the BEC
    377(1)
    3.4 Raptor codes in standards
    378(1)
    4 Extensions to noisy channels
    378(4)
    4.1 The additive white Gaussian noise channel
    378(2)
    4.2 Fading channels
    380(1)
    4.3 Other channels
    381(1)
    4.4 Link to fixed rate counterparts
    381(1)
    5 Advanced sparse-graph based rateless coding schemes
    382(4)
    5.1 LT/Raptor codes extensions
    382(3)
    5.2 Other rateless coding schemes: beyond sparse-graph codes
    385(1)
    6 Applications of rateless coding
    386(13)
    6.1 Rateless coding versus IR-HARQ
    386(1)
    6.2 Multimedia communications and broadcasting
    387(1)
    6.3 Wireless networks and relays
    387(1)
    6.4 Distributed storage and data dissemination
    387(1)
    6.5 Source and source-channel coding
    387(1)
    References
    387(12)
    Chapter 9 An Introduction to Distributed Channel Coding
    399(52)
    1 Introduction
    400(3)
    1.1 Distributed channel coding
    402(1)
    1.2 Outline of this chapter
    402(1)
    1.3 Notations
    403(1)
    2 The three-node relay channel
    403(13)
    2.1 Basic model
    403(2)
    2.2 Relaying strategies
    405(1)
    2.3 Fundamental coding strategies for decode-and-forward relaying
    406(10)
    3 Distributed coding for the three-node relay channel
    416(20)
    3.1 LDPC code designs for the relay channel
    416(17)
    3.2 Distributed turbo-codes and related code structures
    433(3)
    4 Relaying with uncertainty at the relay
    436(2)
    4.1 Compress-and-forward relaying
    437(1)
    4.2 Soft-information forwarding and estimate-and-forward
    438(1)
    5 Cooperation with multiple sources
    438(5)
    5.1 Two-user cooperative network: coded cooperation
    438(2)
    5.2 Multi-source cooperative relay network
    440(3)
    6 Summary and conclusions
    443(8)
    Acknowledgment
    444(1)
    References
    444(7)
    Chapter 10 Space-Time Block Codes
    451(46)
    1 Introduction and preliminaries
    452(5)
    2 STBCs with low ML decoding complexity
    457(6)
    2.1 Encoding complexity, decoding complexity and diversity gain
    458(5)
    3 Full-rate full-diversity STBCs
    463(5)
    3.1 STBCs from division algebras
    464(3)
    3.2 Embedding cyclic division algebras into matrices over the maximal cyclic subfield
    467(1)
    4 Perfect space-time block codes
    468(4)
    5 Diversity and multiplexing gain trade-off of space-time codes
    472(6)
    6 Space-time codes for asymmetric MIMO systems
    478(4)
    6.1 Fast-decodable MIDO codes with large coding gain
    478(2)
    6.2 DMT-optimal LSTBC-schemes for asymmetric MIMO systems
    480(2)
    7 Distributed space-time codes
    482(6)
    7.1 Communication with relays
    482(4)
    7.2 Space-time codes for wireless two-way relaying
    486(2)
    8 Conclusion
    488(9)
    References
    488(9)
    Chapter 11 Coded Modulation
    497(38)
    1 Introduction
    498(1)
    2 Preliminaries
    499(6)
    2.1 Gaussian and Rayleigh fading channels
    499(1)
    2.2 Capacity of signal sets over the Gaussian channel
    499(2)
    2.3 Overview of coded modulation schemes
    501(3)
    2.4 Performance measure
    504(1)
    3 Trellis coded modulation
    505(7)
    3.1 Set partitioning
    506(1)
    3.2 Encoder and decoder for trellis codes
    507(4)
    3.3 Concatenated trellis coded modulation
    511(1)
    4 Multilevel codes and multistage decoding
    512(10)
    4.1 Multilevel codes
    513(1)
    4.2 Multistage decoding
    513(3)
    4.3 Code design for multilevel codes and multistage decoding
    516(3)
    4.4 Iterative decoding of multilevel codes
    519(1)
    4.5 Multilevel codes for unequal error protection
    520(2)
    5 Bit-interleaved coded modulation
    522(13)
    5.1 Encoding of BICM
    522(1)
    5.2 Decoding BICM
    522(2)
    5.3 BICM capacity and capacity-approaching codes
    524(1)
    5.4 BICM with iterative decoding
    525(2)
    5.5 Shaping and BICM
    527(1)
    References
    528(7)
    Chapter 12 Joint Source-Channel Coding and Decoding
    535(48)
    1 Why joint source-channel coding/decoding
    536(1)
    2 Joint source-channel decoding basics
    537(10)
    2.1 Various types of redundancy
    538(2)
    2.2 Decoders to exploit the redundancy
    540(2)
    2.3 Reducing the decoding complexity
    542(5)
    3 Joint source-channel coding basics
    547(5)
    3.1 OPTA
    548(1)
    3.2 Simple (counter-)example
    549(1)
    3.3 To code or not to code
    550(2)
    4 Modified source encoders
    552(10)
    4.1 Variable-length error-correcting codes
    552(3)
    4.2 Redundant signal representations
    555(5)
    4.3 Hierarchical and high-density constellations
    560(2)
    5 Accounting for the presence of a network
    562(8)
    5.1 Redundancy in the protocol stack
    562(1)
    5.2 Protocol-assisted channel decoding
    563(2)
    5.3 Reliable header recovery
    565(1)
    5.4 Reliable burst segmentation
    566(4)
    6 Conclusion
    570(13)
    References
    570(13)
    Chapter 13 Hardware Design and Realization for Iteratively Decodable Codes
    583(70)
    1 Introduction
    584(1)
    2 Standard implementation
    585(14)
    2.1 Quantization of input LLR
    586(1)
    2.2 Standard turbo decoder architecture
    587(6)
    2.3 Standard LDPC decoder architecture
    593(6)
    3 Low complexity decoder
    599(9)
    3.1 Internal precision optimization
    600(1)
    3.2 Precision optimization in turbo decoder
    600(1)
    3.3 Sliding-window technique in turbo decoder
    601(1)
    3.4 Algorithm simplifications
    602(6)
    3.5 Scheduling of Turbo-Code
    608(1)
    4 High throughput architectures
    608(11)
    4.1 Basic solutions to increase decoding speed
    609(1)
    4.2 Average vs. worst case number of iteration
    610(1)
    4.3 Parallel error-free memory access
    610(5)
    4.4 High-speed Turbo-Code
    615(2)
    4.5 High-speed LDPC code
    617(2)
    5 Energy efficient architectures
    619(12)
    5.1 General purpose methods
    620(5)
    5.2 Application-specific methods
    625(6)
    6 Exotic designs
    631(3)
    6.1 Analog decoders
    631(1)
    6.2 Stochastic decoders
    632(2)
    6.3 Conclusion
    634(1)
    7 A survey of relevant implementations
    634(7)
    7.1 High throughput implementations
    635(1)
    7.2 Low energy and low area implementations
    636(1)
    7.3 Flexible decoders
    637(4)
    7.4 Hardware accelerators
    641(1)
    8 Conclusion
    641(12)
    References
    642(11)
    Subject Index 653
    David Declercq was born in June 1971. He graduated his PhD in Statistical Signal Processing 1998, from the University of Cergy-Pontoise, France. He is currently full professor at the ENSEA in Cergy-Pontoise, and is the general secretary of the National GRETSI association, and Senior member of the IEEE. He is currently the recipient of junior position at the "Institut Universitaire de France". His research topics lie in digital communications and error-correction coding theory. He worked several years on the particular family of LDPC codes, both from the code and decoder design aspects.Since 2003, he developed a strong expertise on non-binary LDPC codes and decoders in high order Galois fields GF(q). A large part of his research projects are related to non-binary LDPC codes. He mainly investigated two directions: the design of GF(q) LDPC codes for short and moderate lengths, and the simplification of the iterative decoders for GF(q) LDPC codes with complexity/performance tradeoff constraints. David Declercq published more than 35 papers in major journals (IEEE-Trans. Commun., IEEE-Trans. Inf. Theo., Commun. Letters, EURASIP JWCN), and more than 100 papers in major conferences in Information Theory and Signal Processing. Marc Fossorier's research interests include decoding techniques for linear codes, cryptography, communication algorithms and statistics. Dr. Fossorier became IEEE Fellow in 2006 and he served as Editor for the IEEE Transactions on Information Theory from 2003 to 2006, as Editor for the IEEE Transactions on Communications from 1996 to 2003, as Editor for the IEEE Communications Letters from 1999 to 2007, and as Treasurer of the IEEE Information Theory Society from 1999 to 2003.From 2002 to 2007, he was an elected member of the Board of Governors of the IEEE Information Theory Society which he served as Second and First Vice-President. He was Program Co-Chairman for the 2007 International Symposium on Information Theory (ISIT), the 2000 International Symposium on Information Theory and Its Applications (ISITA) and Editor for the Proceedings of the 2006, 2003 and 1999 Symposium on Applied Algebra, Algebraic Algorithms and Error Correcting Codes (AAECC). Ezio Biglieri received his formal training in Electrical Engineering at Politecnico di Torino (Italy), where he received his Dr. Engr. degree in 1967. Before being an Honorary Professor at University Pompeu Fabra, he was a Professor at Università di Napoli (Italy), at Politecnico di Torino (Italy), and at UCLA (USA). He has held visiting positions with Bell Labs (USA), the École Nationale Supérieure des Télécommunications (Paris, France), the University of Sydney (Australia), the Yokohama National University (Japan), Princeton University (USA), the University of South Australia, the Munich Institute of Technology (Germany), the National University of Singapore, the National Taiwan University, the University of Cambridge (U.K.), ETH Zurich (Switzerland), and Monash University Melbourne (Australia). Among other honors, in 2000 he received the IEEE Third-Millennium Medal and the IEEE Donald G. Fink Prize Paper Award, in 2001 the IEEE Communications Society Edwin Howard Armstrong Achievement Award, in 2004, 2012, and 2015 the Journal of Communications and Networks Best Paper Award, in 2012 the IEEE Information Theory Society Aaron D. Wyner Distinguished Service Award, and in 2021 the IEEE Communications Society Heinrich Hertz Award. He is a Life Fellow of the IEEE.