Preface |
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Acknowledgments |
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1 Regulators and Power Converters |
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1 | (38) |
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1 | (10) |
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1.1.1 Input Power Supply Noise Rejection |
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2 | (1) |
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1.1.2 Load Noise Rejection |
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3 | (1) |
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1.1.3 Topologies of Linear Regulators |
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4 | (3) |
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1.1.4 High Dropout Regulator |
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7 | (2) |
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1.1.5 Low Dropout Regulator |
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9 | (2) |
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1.2 Switch Mode Power Supply |
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11 | (18) |
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11 | (6) |
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17 | (6) |
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1.2.3 Split-π Converter (Boost--Buck Converter) |
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23 | (1) |
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1.2.4 Inverting Converter |
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23 | (6) |
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29 | (8) |
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1.3.1 Positive Charge Pump (Step-Up Converter) |
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29 | (3) |
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1.3.2 Negative Charge Pump (Inverting Converter) |
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32 | (3) |
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1.3.3 Charge Pump LDO (Step-Down Converter) |
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35 | (2) |
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37 | (2) |
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2 Charge Pump Design Specifications and Design Metrics |
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39 | (16) |
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2.1 Charge Pump Design Specifications |
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39 | (9) |
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39 | (3) |
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42 | (1) |
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2.1.3 Input Supply Voltage Range |
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43 | (1) |
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2.1.4 Input Supply Current Capability |
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44 | (1) |
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2.1.5 Output Supply Voltage Range |
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44 | (2) |
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2.1.6 Output Supply Current Capability |
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46 | (1) |
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2.1.7 Output Supply Noise |
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47 | (1) |
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2.2 Charge Pump Design Metrics |
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48 | (5) |
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48 | (1) |
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2.2.2 Charge Pump Power Efficiency |
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49 | (3) |
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52 | (1) |
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53 | (1) |
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53 | (2) |
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3 Single-Stage Charge Pump |
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55 | (54) |
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3.1 Basic Modeling of Charge Pump |
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55 | (15) |
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56 | (3) |
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3.1.2 Capacitive Coupling, Charge Transfer, and Diode Isolation |
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59 | (6) |
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3.1.3 Charge Pump Design with VT Cancellation |
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65 | (1) |
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3.1.4 IV Curve of VT Cancellation Scheme |
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66 | (1) |
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67 | (2) |
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3.1.6 P-Channel versus N-Channel Isolation Device |
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69 | (1) |
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3.2 Basic Cross-Coupled Pair Voltage Doubler |
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70 | (15) |
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70 | (1) |
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3.2.2 Nonoverlapping Clock Phases |
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71 | (1) |
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3.2.3 Precharge Phase versus Coupling Phase |
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72 | (4) |
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76 | (1) |
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76 | (3) |
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3.2.6 Architecture Limitations |
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79 | (6) |
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3.3 Cross-Coupled Pair Voltage Doubler: Parallel Stage VT Cancellation on Output Stages |
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85 | (13) |
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86 | (9) |
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3.3.2 Architecture Limitations |
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95 | (3) |
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3.4 Cross-Coupled Pair Voltage Doubler: Parallel Stage VT Cancellation on Input Stage |
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98 | (4) |
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99 | (3) |
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3.4.2 Architecture Limitations |
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102 | (1) |
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3.5 Cross-Coupled Pair Voltage Doubler: Parallel Stage VT Cancellation Optimum Design |
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102 | (4) |
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103 | (3) |
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106 | (1) |
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107 | (2) |
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109 | (18) |
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4.1 Positive Charge Pump with Diode Isolation |
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109 | (5) |
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109 | (1) |
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109 | (3) |
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112 | (1) |
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113 | (1) |
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4.2 Negative Charge Pump with Diode Isolation |
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114 | (4) |
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114 | (1) |
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115 | (2) |
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117 | (1) |
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118 | (1) |
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4.3 Parallel Stage VT Cancellation |
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118 | (4) |
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118 | (1) |
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119 | (2) |
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121 | (1) |
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122 | (1) |
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4.4 Self-adaptive Charge Pump |
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122 | (2) |
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122 | (2) |
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4.5 Four-Phase Charge Pump |
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124 | (2) |
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124 | (1) |
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4.5.2 Four-Phase Charge Pump without Clock Phase Overlap |
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125 | (1) |
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126 | (1) |
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5 Charge Pump Clock Driver |
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127 | (20) |
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5.1 Pump Clock Driver Design |
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127 | (6) |
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5.1.1 Supply of Pump Clock Driver |
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127 | (2) |
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5.1.2 Delay of Internal Buffering Stage |
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129 | (1) |
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5.1.3 Final Stage of Clock Buffer and Buffering Technique |
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130 | (3) |
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133 | (7) |
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134 | (1) |
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135 | (1) |
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136 | (2) |
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138 | (2) |
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5.3 Pump Clock Driver with Stacking Capacitors |
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140 | (6) |
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140 | (6) |
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146 | (1) |
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6 Charge Pump Stability Analysis |
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147 | (22) |
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147 | (1) |
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148 | (9) |
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6.2.1 DC or Low-Frequency Response |
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149 | (1) |
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6.2.2 High-Frequency Response |
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149 | (1) |
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6.2.3 First-Order Negative Feedback System |
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150 | (1) |
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6.2.4 Second-Order Negative Feedback System |
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151 | (2) |
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6.2.5 Higher-Order Negative Feedback System |
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153 | (1) |
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154 | (3) |
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6.3 Stability and Compensation for Charge Pump |
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157 | (10) |
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6.3.1 Charge Pump with On/Off Regulation |
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158 | (2) |
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6.3.2 Charge Pump with Dynamic Voltage Scaling |
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160 | (7) |
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167 | (2) |
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7 Charge Pump Design, Regulation, and Control by Examples |
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169 | (40) |
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7.1 Resistive Divider Feedback Control |
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169 | (4) |
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169 | (2) |
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171 | (2) |
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7.2 Capacitive Divider Feedback Control |
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173 | (3) |
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175 | (1) |
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175 | (1) |
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7.2.3 Charge Conservation |
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175 | (1) |
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7.3 Capacitive Divider Feedback without Refreshing Interruption |
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176 | (3) |
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179 | (3) |
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179 | (1) |
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180 | (2) |
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182 | (4) |
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7.5.1 Initialization Phase |
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182 | (2) |
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184 | (1) |
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185 | (1) |
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185 | (1) |
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7.6 Alternative Hybrid Regulation |
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186 | (3) |
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7.6.1 Initialization Phase |
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187 | (1) |
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188 | (1) |
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189 | (1) |
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7.7 Dynamic Frequency Scaling |
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189 | (3) |
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7.7.1 Dynamic Frequency Scaling with Predefined Operations |
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189 | (1) |
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7.7.2 Dynamic Frequency Scaling with Feedback Control |
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190 | (2) |
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7.8 Dynamic Voltage Scaling |
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192 | (4) |
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7.8.1 Continuous Pump Clock Amplitude Scaling |
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194 | (1) |
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7.8.2 Quantized Pump Clock Amplitude Scaling |
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195 | (1) |
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7.9 High-Efficiency Charge Pump Regulator |
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196 | (5) |
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7.9.1 Initialization Phase |
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198 | (1) |
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199 | (2) |
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7.10 RC-Based VT Cancellation |
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201 | (4) |
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201 | (1) |
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7.10.2 High-Pass Function |
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202 | (1) |
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202 | (3) |
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7.11 Charge Pump Clock Equalization |
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205 | (3) |
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208 | (1) |
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8 Charge Pump Applications |
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209 | (26) |
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8.1 Oversampling Charge Pump ADC |
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210 | (7) |
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213 | (1) |
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214 | (1) |
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8.1.3 Oversampling Charge Pump ADC |
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215 | (2) |
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8.2 Sigma-Delta Oversampling Charge Pump ADC |
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217 | (4) |
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8.3 Dynamic Output Noise Optimization Using Charge Pump-Based Current ADC |
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221 | (6) |
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8.4 Dynamic Power Efficiency Optimization Using Charge Pump ADC |
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227 | (4) |
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8.5 Dynamic IR Drop Compensation with Variable Current Load |
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231 | (2) |
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233 | (2) |
Index |
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