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Circuits for Emerging Technologies Beyond CMOS

New exciting opportunities are abounding in the field of body area networks, wireless communications, data networking, and optical imaging. In response to these developments, top-notch international experts in industry and academia present Circuits at the Nanoscale: Communications, Imaging, and Sensing. This volume, unique in both its scope and its focus, addresses the state-of-the-art in integrated circuit design in the context of emerging systems.

A must for anyone serious about circuit design for future technologies, this book discusses emerging materials that can take system performance beyond standard CMOS. These include Silicon on Insulator (SOI), Silicon Germanium (SiGe), and Indium Phosphide (InP). Three-dimensional CMOS integration and co-integration with Microelectromechanical (MEMS) technology and radiation sensors are described as well. Topics in the book are divided into comprehensive sections on emerging design techniques, mixed-signal CMOS circuits, circuits for communications, and circuits for imaging and sensing.

Dr. Krzysztof Iniewski is a director at CMOS Emerging Technologies, Inc., a consulting company in Vancouver, British Columbia. His current research interests are in VLSI ciruits for medical applications. He has published over 100 research papers in international journals and conferences, and he holds 18 international patents granted in the United States, Canada, France, Germany, and Japan. In this volume, he has assembled the contributions of over 60 world-reknown experts who are at the top of their field in the world of circuit design, advancing the bank of knowledge for all who work in this exciting and burgeoning area.

Arvustused

Written by top-notch experts, Circuits at the Nanoscale: Communications, Imaging, and Sensing addresses the state of the art in CMOS circuit design in the context of system opportunities. This book explores materials such as SiGe, carbon nanotubes, and quantum dots that can potentially take system performance beyond traditional CMOS. Because CMOS circuit implementation is key to understanding emerging technologies, several chapters focus on this area, including low power circuit implementations for microprocessor applications and circuit implementations for biomedical space. The text also discusses such topics as digital radio processing for wireless communications and circuits for medical imaging.

Editor ix
Contributors xi
PART I CMOS Technology at the Nanoscale
CMOS: An Emerging Technology System Driver
3(8)
Paul Rousseau
CMOS Rise to Dominance: A Very Brief History
3(1)
CMOS Is Everywhere
4(2)
Logic-Based Embedded DRAM CMOS
6(1)
Logic-Based Embedded Flash CMOS
7(1)
High-Voltage CMOS
7(1)
CMOS Image Senson
8(1)
RF CMOS and SiGe BiCMOS
8(1)
Other Technology Considerations
8(1)
Automotive
8(1)
MEMS
8(1)
SoC versus SiP
9(1)
Conclusions
9(1)
References
9(2)
CMOS Manufacturability
11(14)
Artur Balasinski
Introduction: Two Directions for Techonology Development
11(1)
Continuous Shrinking: Memories and Logic
12(3)
Lithography and OPC: Closing the Subwavelentfh Gap
12(1)
MOSFETs
13(2)
New Materials for Interconnects
15(1)
Tehnologies for New Applications: System-on-Chip and Analog/RF
15(8)
Process Challenges
15(1)
Variability Reduction for MOSFETs and Passive Elements
16(7)
Conclusions
23(1)
References
23(2)
Variability in Deeply Scaled CMOS
25(14)
Liang-Teck Pang
Borivoje Nikolic
Introduction
25(3)
Characterization of Variations
25(2)
Lithography-Induced Variations
27(1)
Test Chip
28(3)
Measurement Results
31(5)
Effects of Layout on Frequency and Leakage
31(2)
D2D Variation
33(1)
WID Variations
34(1)
Inferring Process Parameters
34(2)
Conclsion
36(1)
Acknowledgements
36(1)
References
36(3)
Water-Level Three-Dimensional Integration for Advanced CMOS systems
39(14)
Ronald J. Gutmann
Jian-Qiang Lu
Introduction
39(1)
Wafter-Level 3D Technology Platforms
40(4)
Digital IC Applications
44(2)
Analog/Mixed-Signal Applications
46(3)
Unique System Architectures
49(1)
Future Drivers for Wafer-Level 3D in IC Manufacturing
49(2)
Technology Drivers
50(1)
Design Drivers
50(1)
Equipment Infrastructure Drivers
50(1)
Industryu Infrastructure Drivers
50(1)
Predictions
51(1)
Acknowledgements
51(1)
References
51(2)
CMOS SOI Memory Design Technology
53(22)
Kazutami Arimoto
Fukashi Morishita
Background and Future Trends
53(1)
Low-Power and high-Speed SOI Circuit Design
54(5)
Demands of Both Low-Power and High-Speed Operation
54(1)
Dynamic Body-Control Technique
55(2)
Automatic Sources/Body-Control Technique
57(2)
SOI Memory Technologies
59(11)
Capacitorless Memory Design
59(1)
TTRAM Cell Operation
59(3)
TTRAM Array Architecture
62(4)
Implementation of TTRAM
66(1)
Scalable Functions of TTRAM
66(3)
Actively Body-Bias Controlled SRAM
69(1)
Feature SOI Technology Trend
70(2)
References
72(3)
SiGe Technology
75(20)
Marco Racanelli
Introduction
75(1)
SiGe Devices: The Basics
76(1)
Applications Driving SiGe Development
77(1)
SiGe Performance Roadmap
77(3)
Modern SiGe BiCMOS RF Platform
80(3)
Key Application Trends and Examples
83(8)
Key Wireless RF Circuit Blocks: Low-Noise Amplifier
83(1)
Key Wireless RF Circuit Blocks: Power Amplifier
84(4)
Emerging Applications
88(3)
Conclusions
91(1)
Acknowledgements
91(1)
References
91(4)
PART II Emerging Design Techniques
Offset, Flicker noise, and Ways to Deal with Them
95(22)
Hanspeter Schmid
Introduction
95(1)
What Is Flicker Noise?
96(4)
The Nature of Flicker Noise
97(1)
Memory in Systems
98(1)
Memories in MOSFETs and Other Electronic Devices
98(2)
Memory and Correlation
100(1)
Flicker Noise Is Offset Extended In Frequency
100(1)
Techniques to Reduce Flicker Noise
100(1)
Switched-Capacitor Techniques
100(3)
Sampled Noise in SC Circuits
102(1)
Bias Switching and Large-Scale Excitation
103(2)
Chopping
105(4)
Conventional Chopper Amplifier
106(1)
Multipath Chopper Amplifiers
107(1)
Chopping in Sampled-Data Systems
108(1)
Correlated Double Sampling and Auto-Zero Techniques
109(4)
Switched-Capacitor Comparator with CDS
110(1)
Switched-Capacitor Amplifier with CDS
111(1)
Correlated Double Sampling in Sampled Systems
112(1)
Correlated Double Sampling Combined with Large-Scale Excitation
112(1)
Conclusion
113(1)
Appendix
113(1)
References
114(3)
Design of Wideband Amplifiers in CMOS
117(18)
David J. Allstot
Sudip Shekhar
Jeffrey S. Walling
Introduction
117(2)
Shunt Peaking and Bridged-Shunt Peaking
119(1)
Series Peaking
120(2)
Bridged-Shunt-Series Peaking
122(1)
Asymmetric T-Coil Peaking
123(2)
Design of High-Speed Wideband Differential Amplifiers
125(1)
Effects of Other Device Parasitics
126(3)
Effects of Cgd
127(1)
Effects of gds
128(1)
Measurement Results
129(3)
Measurement Methodology
129(1)
Measured Data
130(2)
Conclusions
132(1)
References
132(3)
CMOS Active Transformers and Their Applications
135(14)
Fei Yuan
Introduction
135(1)
Active Inductors
136(2)
Configuration and Characteristics
136(1)
Frequency Range
137(1)
Quality Factor
138(1)
CMOS Active Inductors
138(1)
Active Transformers
138(7)
Configuration
138(1)
Characterization
139(1)
Self and Mutual Inductances
140(1)
Turn Ration
140(1)
Coupling Factors
141(1)
Voltage Ratio
141(1)
Current Ratio
142(1)
Nonideal Active Transformer
142(2)
Quality Factor
144(1)
CMOS Active Transformers
144(1)
Applications of DMOS Active Transformers
145(2)
Conclusions
147(1)
References
147(2)
High-Performance Leakage/Variation-Tolerant Circuit Technologies for 45 nm and Below
149(10)
Amit Agarwal
Ram Krishnamurthy
Introduction
149(2)
Register File Organization
151(2)
Bitline Leakage Robustness
153(1)
Leakage/Process-Tolerant Register File Circuits
154(2)
Woedline Underdrive Local Bitline
154(1)
NAND Merge Skew Local Bitline
155(1)
Process Variation Compensating Dynamic Local Bitline
155(1)
Summary
156(1)
Refrences
157(2)
Soliton and Nonlinear Wave Electronics
159(28)
David S. Ricketts
Xiaofeng Li
Donhee Ham
Introduction
159(2)
Nonlinear Transmissions Line and Electrical Solitons
161(3)
Solitons
161(1)
Electrical Solitons
161(1)
Propagation and Collision of Electrical Solitons
162(1)
Forming and Damping of Electrical Solitons
162(2)
The Electrical Soliton Oscillator
164(4)
Soliton Oscillator Topology
164(1)
Oscillation Instability Mechanisms
164(3)
Taming Electrical Solitons with an Amplifier
167(1)
Design Procedure
168(1)
First Prototype---Discrete Proof of Concept
169(8)
Prototype Implementation
169(2)
Experimental Results
171(1)
Adaptive Bias Control
171(1)
Startup Soliton Dynamics
172(1)
Perturbation Rejection
172(1)
Steady-State Soliton Oscillation
173(1)
Spatial Soliton Propagation in Steady State
173(1)
In-Depth Experimental Studies on the Soliton Oscillator Dynamics
174(1)
Existence of a Limit Cycle
174(1)
Spatial Dynamics Revisited
175(2)
Second Prototype---Discrete Microwave Soliton Oscillator
177(2)
Third Prototype---CMOS Electrical Soliton Oscillator
179(2)
Chip-Scale Implementation
179(1)
Measurement Results
180(1)
Soliton Oscillator Summary and Future Directions
181(1)
Chaotic Soliton Oscillator
182(1)
Conclusion
182(1)
Acknowledgments
183(1)
References
183(4)
PART III Mixed-Signal CMOS Circuits
Current Steering Digital-to-Analog Converters
187(26)
Douglas A. Mercer
Digital-to-Analog Converter Basics
187(5)
Common D/A Architectures
189(1)
Voltage Divider
189(1)
Segmented DACs
190(1)
R-2R Ladder DACs
190(1)
Delta-Sigma Architecture
191(1)
Manufacturing Processes
192(1)
Current-Mode DACs in CMOS
192(1)
Power Dissipation
193(1)
Static Errors and Matching
194(3)
Self-Calibration
197(2)
Finite Output Impedance
199(2)
Similarities between DAC and Flash ADC
201(1)
Digital Data Pattern-Dependent Noise
202(1)
Data-Dependent Clock Loading
203(2)
Switch Gate Drive
205(4)
Return-to-Zero Switching
209(1)
Quad Switching/Constant Data Activity
209(2)
Conclusions
211(1)
References
211(2)
High-Speed, Low-Power CMOS A/D Converter for Software Radio
213(12)
James S. Haslett
Abdel-Fattah S. Yousif
Introduction
213(1)
ADC Performance Scaling
214(2)
High-Speed Subsampling and Oversampling ADCs
216(1)
High-Speed and Low-Resolution ADC Architectures
217(4)
Flash ADC Architecture
217(3)
Time-Based ADC Architecture
220(1)
High-Resolution and Multi-GHz ADC Architectures
221(2)
Conclusions
223(1)
References
223(2)
Energy-Efficientg ADC Topology Enabled with Asynchronous Techniques
225(20)
Shuo-Wei Mike Chen
Introduction
225(1)
Power Efficiency of ADC Architecture
226(1)
Asynchronous Processing
227(3)
Design Example of a 6-bit 600 Ms/s Asynchronous ADC
230(8)
Architecture
230(1)
Dynamic Comparator and Ready Signal
231(1)
Nonbinary Successive Approximation Review
232(1)
Series Nonbinary Capacitive Ladder
232(2)
Digital Calibration Scheme
234(1)
Variable Duty-Cycled Clock
234(2)
High-Speed Digital Logic
236(1)
Measured Results
236(2)
Scaling Trend of an Asynchronous ADC
238(2)
Applications of the Proposed ADC Topology
240(2)
References
242(3)
High-Frequency Filters for Data Communication Applications
245(22)
Manisha Gambhir
Vijay Dhanasekaran
Jose Silva-Martinez
Edgar Sanchez-Sinencio
Introduction
245(1)
Filter Design: Scaling Fundamentals
246(2)
Impedance Scaling
246(1)
Parallel Circuits
247(1)
Frequency Scaling
247(1)
Frequency Scaling Under Constant Noise
248(1)
Power-Noise Product
248(1)
Gm-C Topologies
248(6)
Architectural Considerations
249(2)
Building Blocks and Nonidealities
251(2)
Design Procedure
253(1)
LC Topologies
254(2)
Architectural Considerations
255(1)
Design Considerations
256(1)
Equalizing Filters
256(8)
Boost Filter Architecture Using Gm-C Techniques
258(1)
Boost Filter Architecture Using LC Techniques
259(2)
Gm-C versus LC Structures
261(3)
Conclusions
264(1)
References
264(3)
Continuous Time ΣΔ Modulators
267(22)
Robert Sobot
State of the Art
268(3)
Survey of Published Designs
268(2)
Current Design Trends
270(1)
Basic Principles of ΣΔ Modulators
271(1)
Quantization of a Continuous Signal
271(1)
Quantization Noise
271(1)
SNR of an Ideal A/D Converter
272(1)
Fractional ΣΔ Modulators
272(3)
Theoretical Background
272(1)
ΣΔ Loop Filter Transfer Function
273(1)
Zero-Delay CT BP ΣΔ Modulators
273(1)
Delayed CT BP ΣΔ Modulators
274(1)
CT BP ƒΣΔ Modulator Design
275(4)
Design Architecture
275(1)
gm-C Resonator
276(1)
Design of the gm Stage
277(1)
Comparator
277(1)
Postlayout Simulation
278(1)
Prototype Chip Testing
279(1)
Experimental Results
279(1)
CT BP ƒΣΔ Applications
279(4)
Fractional Delay ΣΔ Upconverter
280(2)
ƒΣΔ-Based PA
282(1)
Summary
283(1)
References
283(6)
PART IV Circuits for Communications
Low-Voltage Nanometer-Scale CMOS RF Front-End Block Design Employing Magnetic Feedback Techniques
289(30)
Yannis Papananos
Georgios Vitzilaios
Gerasimos Theodoratos
Introdution
289(1)
Advances in Low-Voltage CMOS Design
290(1)
Single-Transistor LNA Topologies
290(12)
Limitations of Single-Transistor LNAs
290(1)
Reverse Isolation Enhancement Utilizing Magnetic Feedback
291(2)
Triple Transformer LNA Analysis
293(2)
Stability Issues
295(1)
Multiple Transformer Layout
295(1)
Typical Performance
296(1)
Alternative Method for Reverse Isolation Enhancement
296(6)
LNA Linearization Utilizing Magnetic Feedback
302(7)
Predistorter Topology
303(1)
Shunt Transistor Predistorter
303(1)
Proposed Predistortion Scheme
304(5)
Typical Performance
309(1)
Low-Voltage Mixer Design
309(8)
Conventional Mixer Topology
310(1)
Alternative Mixer Topology
311(3)
Linearization Technique
314(1)
Typical Performance
315(2)
Integrated Transformer Design Methodology
317(1)
Conclusions
317(1)
References
317(2)
InGaP-HBT Power Amplifiers
319(24)
Kazuya Yamamoto
Introduction
319(2)
Power Amplifier Design
321(9)
Basic Bias Circuit Topology
321(3)
Bias Drive and AM-AM/AM-PM Characteristics
324(2)
Bias Circuits and AM-AM/AM-PM Characteristics
326(4)
Recent Power Amplifier Technologies
330(8)
Parallel Amplifier Approach
331(2)
Low-Reference-Voltage Operation Power Amplifier
333(5)
Conclusions
338(1)
References
338(5)
ΔΣDigital-RF Modulation for Adaptive Wideband Systems
343(20)
Albert Jerng
Charles G. Sodini
Introduction
343(2)
Digital-RF Conversion
345(1)
ΔΣ System Architecture
346(1)
LC Bandpass Filter Design
347(9)
Area Considerations
349(1)
Impedance Considerations
349(1)
Resonator Design
349(2)
Prototype 5.25 GHz Filter Design
351(1)
Automatic Tuning Loop
352(1)
Digital Tuning Loop
353(1)
Q-Enhancement
354(2)
Experimental Results
356(1)
Applications for Wideband Digital-RF Modulation
357(3)
Conclusion
360(1)
References
360(3)
Deep-Submicron CMOS Design Challenges When Integrating the RF Front-End and Digital Baseband in a Single-Chip Receiver SoC
363(36)
Adrian Maxim
Introduction
363(1)
Single-Chip Receviver SoC Top Level
364(1)
Spur Coupling in Mixed-Signal Single-Chip Receiver SoCs
365(3)
Front-End LNA Spur Reduction
368(1)
LNA-Mixer Interface Spur Reduction
369(1)
RF Frequency Synthesizer Spur Reduction
370(8)
Low-Noise, High-Supply Rejection Regulators
378(6)
LO Path Spur Rejection
384(2)
Quadrature Generator Spur Reduction
386(1)
IF Path Supply Spur Remixing
387(2)
Digital Core Clock Generation and Spur Management Techniques
389(2)
ADC Spur Reduction
391(1)
Digital Regulator with High-Reverse Rejection Ratio
392(1)
Shielding Considerations of Sensitive Signal Lines
393(1)
Digital Control Lines Spur and Noise Rejection
394(1)
Conclusions
395(1)
References
396(3)
Mitigation of CMOS Device Variability in Digital RF Processor
399(20)
Khurram Waheed
Robert Bogdan Staszewski
Introduction
399(4)
Mismatches in Digital-to-RF-Amplitude Converter
403(5)
Mismatches in Digitally Controlled Oscillator
408(8)
Varactor Structure in Nanoscale CMOS
409(1)
Fully Digital Control of a CMOS Oscillator
410(1)
Modeling of Varactor Mismatches
411(1)
Assessment of Physical Device Mismatches
412(4)
Summary
416(1)
References
416(3)
Front-End Circuits for Multi-Gb/x Chip-to-Chip Links
419(18)
Anthony Chan Carusone
Introduction
419(1)
Applications
420(2)
Parallel Buses
421(1)
Serial Links Over Backplanes
421(1)
Link Modeling
422(5)
Linear Two-Port Networks
422(2)
The Transmission Line
424(1)
Complete Links
425(2)
Equalization
427(4)
Transmit Equalization
427(2)
Receive Equalization
429(1)
Cross Talk
430(1)
Modulation
431(1)
Serial Links
431(1)
Parallel Buses
432(1)
Conclusion
432(1)
Appendix A
433(1)
Impedance Matrices
433(1)
Admittance Matrices
433(1)
Scattering Parameters
434(1)
RLGC Values
434(1)
Acknowledgments
434(1)
References
434(3)
Clock and Data Recovery Circuits
437(20)
Jafar Savoj
Introduction
437(1)
Injection-Locked CDR Circuit
438(1)
Phase-Locked CDR Circuit
439(5)
Full-Rate CDR
440(1)
Linear PD
440(1)
Binary PD
440(1)
Subrate CDR
441(1)
Linear PD
441(1)
Binary PD
442(1)
Aided Frequency Acquisition
443(1)
Phase-Rotating CDR Circuit
444(2)
Fully Digital CDR Circuit
446(2)
LC Oscillators in CDR Circuits
448(2)
Jitter in CDR Circuits
450(2)
Conclusions
452(1)
References
452(5)
PART V Circuits for Imaging and Sensing
Low Power CMOS Imager Circuits
457(28)
Lexander Fish
Orly Yadid-Pecht
Introduction
458(1)
Smart CMOS Image Sensor Architecture
459(4)
Active Pixel Sensor Pixel Array
460(1)
Scanning Circuitry
461(1)
Analog Front End
461(1)
Analog-to-Digital Conversion
462(1)
Reference Circuits
462(1)
Digital Timing
463(1)
Image Processing
463(1)
Sources of Power Dissipation in Image Sensors
463(7)
Sensor Array Power Dissipation
464(2)
Power Dissipation in Scanning Circuitry
466(1)
Analog Front End Power Dissipation
467(1)
Power Dissipation in Analog-to-Digital Conversion
468(1)
Power Dissipation in Bandgap Reference and Current Generators
468(1)
Power Dissipation in Digital Timing and Control Block
468(1)
Power Dissipation in Image Processing
469(1)
Power Reduction in Smart CMOS Image Sensors
470(11)
Power Reduction at the Technology and Device Levels
470(1)
General Considerations
470(1)
Practical Example---Self-Powered Active Pixel Sensors
471(3)
Power Reduction at the Algorithm and Architecture Levels
474(1)
General Considerations
474(1)
Practical Example---Sensor for Multiple Targets Detection and Tracking
475(2)
Power Reduction at the Circuit and Logic Levels
477(1)
Leakage Control
477(1)
Low-Voltage Operation
478(1)
Power-Efficient Digital Control Circuitry
478(1)
Optimization of Sensor Output Chains
478(1)
Practical Example---Wide Dynamic Range Snapshot APS
479(2)
Conclusions
481(1)
References
481(4)
CMOS IMager Array Design, Operation, and Trends
485(18)
Mark Jaffe
John Ellis-Monaghan
Jim Adkisson
Introduction
485(1)
Pixel Evolution
485(6)
Passive Pixel
485(1)
Active 3T Pixel
486(2)
Active 4T Pixel
488(1)
Global Shutter and Specially Pixels
489(2)
Pixel Operation
491(5)
Static State
491(1)
Photodiode Reset
492(1)
Photointegration
493(2)
Correlated Double Sample Readout
495(1)
Pixel Scaling
496(5)
Scaling and Optical Transmission
497(1)
Scaling and Signal Capacity
498(2)
Pixel Scaling and Noise
500(1)
Conclusions
501(1)
References
501(2)
Wide Dynamic Range CMOS Cameras
503(18)
Steve Collins
Bhaskar Choubey
Hsiu-Yu Cheng
Stephen Otim
Introduction
503(1)
Motivation
504(1)
Logarithmic Pixels
505(5)
Logarithmic Pixels with Reset
510(3)
Integrating Pixels with a Logarithmic Response
513(4)
The Future
517(2)
References
519(2)
CMOS Focal Plane Spatially Oversampling Computational Image Sensor
521(18)
Ashkan Olyaei
Roman Genov
Introduction
521(1)
Block-Matrix and Convolutional Transforms
522(3)
Discrete Wavelet Transform: Haar Wavelet Example
523(2)
Architecture
525(1)
Image Acquisition
526(2)
Computational Quantization
528(5)
Sign Unit
528(1)
ΔΣ- Modulated Multiplying ADC
529(1)
ΔΣ- Modulated Weighted Averaging ADC
530(2)
Switch Matrix
532(1)
Digital Accumulation
533(1)
Comparative Example
533(1)
Results
534(3)
Conclusions
537(1)
References
537(2)
Unified Computer Arithmetic for Handheld GPUs
539(22)
Byeong-Gyu Nam
Hyenjung Kim
Hoi-Jun Yoo
Introduction
539(1)
Handheld 3D Computer Graphics
540(2)
3D Graphics Pipeline
540(1)
Geometry Stage
541(1)
Rendering Stage
541(1)
Standard APIs for Handheld 3D Graphics
541(1)
Computer Arithmetic for Handheld GPUs
542(4)
Floating Point Arithmetic
543(2)
Fixed Point Arithmetic
545(1)
Philosophy of Unified Computer Arithmetic
546(1)
Unified Vector and Elementary Function Unit
547(12)
Fixed Point Hybrid Number System
547(1)
Number Converters
548(1)
Logarithmic Converter
548(1)
Antilograrithmic Converter
549(1)
FXP-HNS Unified Arithmetic Unit
549(2)
Vector Operations
551(2)
Elementary Functions
553(4)
Evaluations
557(2)
Conclusions
559(1)
References
559(2)
Sense Circuits for Integrated Sensors
561(14)
Sitaraman V. Iyer
Hasnain Lakdawala
Introduction
561(1)
Sensor and Circuit Nonidealities
562(2)
Noise
562(1)
Offset
563(1)
Gain Variation
563(1)
Temperature Effects
564(1)
Techniques to Reduce Offset and Low-Frequency Noise
564(4)
Sensor Techniques
564(1)
Chopper Stabilization
565(1)
Correlated Double Sampling
566(1)
Gain Calibration
567(1)
Temperature Compensation
567(1)
Hall Effect Sensors
568(1)
Sensing Mechanism
568(1)
Nonidealities in Hall Sensors
568(1)
Inertial Sensors
569(3)
Accelerometers and Gyroscopes
569(2)
Circuit Techniques
571(1)
Conclusions
572(1)
References
572(3)
Detector Interface Circuits for X-Ray Imaging
575(26)
Pawel Grybos
Introduction
575(1)
Detector Array
576(1)
Semiconductor Material for Detector
576(1)
Detector Geometry
576(1)
Requirements and Limitations of the Front-End Electronics for Digital X-Ray Imaging
577(2)
Charge-Sensitive Amplifier
579(6)
Noise Optimization
579(4)
Reset Block
583(2)
Shaper Stage
585(1)
Analog-to-Digital Conversion in Multichannel IC
586(2)
Physical Implementation Aspects
588(3)
Crosstalk in Mixed-Mode IC
588(1)
Mathing Performance
589(2)
Examples of Multichannel Readout ICs
591(6)
DEDIX IC---Fast Digital X-Ray Imaging
591(2)
Peak Detector Derandomizer ASIC
593(1)
Medipix2 IC
594(2)
PILATUS IC
596(1)
References
597(4)
CMOS Systems and Interfaces for Microgyroscopes
601(22)
Ajit Sharma
Mohammad F. Zaman
Farrokh Ayazi
Introduction
601(2)
Principle of Operation
602(1)
Applications of MEMS Gyroscopes
602(1)
Performance Metrics
603(1)
Resolution
603(1)
Scale Factor
603(1)
Zero Rate Output and Bias Stability
604(1)
Bandwidth and Dynamic Range
604(1)
Review of Micromachined Gyroscopes
604(2)
Electronic Control Systems in Gyroscopes
606(3)
Drive Loop
608(1)
Quadrature Nulling
608(1)
Mode-Matching
608(1)
Sense Channel
608(1)
Self-Test and Trim
609(1)
Case Study---Mode-Matched Tuning Fork Gyroscope
609(10)
Challenges and Trade-offs in Microgyro Interfacing
610(1)
Review of Microgyro Front-Ends
611(1)
Transimpedance Front-Ends for Motional Current Detection
612(1)
Low-Noise Wide Dynamic Range T-Network TIA
613(1)
Design Considerations
613(2)
Characterization Results
615(1)
Drive and Sense Channels
616(2)
System Integration
618(1)
Future Directions and Conclusions
619(2)
References
621(2)
Analog Front End for a Micromachined Probe Storage Device
623(22)
Christoph Hagleitner
Tony Bonaccio
Hugo Rothuizen
Jan Lienemann
Dorothea Wiesmann
Giovanni Cherubini
Jan G. Korvink
Evangelos Eleftheriou
Introduction
623(2)
Analog Front-End Chip Architecture
625(3)
Read Channel
626(1)
The Modeling Approach
627(1)
Cantilever Model
628(7)
Electrical/Thermal Model
630(2)
Mechanical/Electrostatic Model
632(3)
Model of Tip-Surface Contact
635(1)
Noise Model
635(1)
Verification of Cantilever Model
635(2)
Electrical/Thermal Model
635(1)
Electrostatic/Mechanical Model
635(2)
Analog Front End Design
637(3)
Input Stage
637(1)
Model-based Optimization of Power/Signal-to-Noise Ratio
638(2)
Experimental Results
640(1)
Summary
641(1)
Acknowledgments
641(1)
References
641(4)
Index 645
CMOS Emerging Technologies Inc., Vancouver, British Columbia
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