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E-raamat: CMOS Analog Design Using All-Region MOSFET Modeling

(Universidade Federal de Santa Catarina, Brazil), (Universidade Federal de Santa Catarina, Brazil)
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  • Ilmumisaeg: 28-Jan-2010
  • Kirjastus: Cambridge University Press
  • Keel: eng
  • ISBN-13: 9780511795619
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  • Ilmumisaeg: 28-Jan-2010
  • Kirjastus: Cambridge University Press
  • Keel: eng
  • ISBN-13: 9780511795619
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Comparing bipolar technology briefly but otherwise not considering it, Schneider and Galup-Montoro (both electrical engineering, Federal U. of Santa Catarina, Brazil) focus on analog MOS (metal-oxide-semiconductor) circuits at the transistor level. They use an accurate but simple MOS transistor model for design, in order to reduce the distance between hand design and simulation results. Instead of the usual separate analytical formulas for the strong-inversion and weak-inversion operation regions of a building block, they provide simple formulas that are valid in all operation regions, including moderate inversion. The unified design is particularly suitable for analog design in advanced complementary MOS (CMOS) technologies. Among their topics are temporal and spatial fluctuations in MOSFETs (MOS field-effect-transistors), current mirrors, basic gain stages, operational amplifiers, and fundamentals of sampled-data circuits. The text is suitable for analog CMOS design courses. Annotation ©2010 Book News, Inc., Portland, OR (booknews.com)

Covering the essentials of analog circuit design, this book takes a unique design approach based on a MOSFET model valid for all operating regions, rather than the standard square-law model. Opening chapters focus on device modeling, integrated circuit technology, and layout, whilst later chapters go on to cover noise and mismatch, and analysis and design of the basic building blocks of analog circuits, such as current mirrors, voltage references, voltage amplifiers, and operational amplifiers. An introduction to continuous-time filters is also provided, as are the basic principles of sampled-data circuits, especially switched-capacitor circuits. The final chapter then reviews MOSFET models and describes techniques to extract design parameters. With numerous design examples and exercises also included, this is ideal for students taking analog CMOS design courses and also for circuit designers who need to shorten the design cycle.

The essentials of analog circuit design with a unique all-region MOSFET modeling approach.

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The essentials of analog circuit design with a unique all-region MOSFET modeling approach.
Preface xv
Introduction to analog CMOS design
1(25)
Analog design
1(2)
The need for analog design
1(1)
Tradeoffs in analog design
2(1)
The Importance of component modeling
2(1)
Bipolar and metal-oxide-semiconductor field-effect transistors
3(13)
p-n Junctions
3(2)
Bipolar junction transistors
5(2)
MOS field-effect transistors
7(7)
Important differences between BJTs and MOSFETs
14(2)
Analog bipolar and MOS integrated circuits
16(5)
Analysis and design of integrated circuits
16(1)
Design of common-emitter and common-source amplifiers
17(4)
Problems
21(3)
References
24(2)
Advanced MOS transistor modeling
26(62)
Fundamentals of the MOSFET model
26(19)
Electrons and holes in semiconductors
26(2)
The two-terminal MOS structure
28(3)
Accumulation, depletion, and inversion (for p-type substrates)
31(1)
The small-signal equivalent circuit of the two-terminal MOS (for p-type substrates)
32(2)
The three-terminal MOS structure and the unified charge-control model (UCCM)
34(4)
The pinch-off voltage
38(1)
The Pao-Sah exact I-V model
39(2)
A charge-sheet formula for the current
41(1)
A charge-control compact model
41(1)
Threshold voltage
42(3)
A design-oriented MOSFET model
45(12)
Forward and reverse components of the drain current
45(3)
Universal dc characteristics
48(3)
MOSFET operation in weak and strong inversion
51(2)
Small-signal transconductances
53(4)
Dynamic MOSFET models
57(11)
Stored charges
57(2)
Capacitive coefficients
59(3)
Capacitances of the extrinsic transistor
62(1)
A non-quasi-static small-signal model
62(3)
A quasi-static small-signal model
65(2)
The intrinsic transition frequency
67(1)
Short-channel effects in MOSFETs
68(9)
Effective mobility
68(1)
Velocity saturation
69(2)
Channel-length modulation
71(1)
Drain-induced barrier lowering
72(1)
Output conductance in saturation
73(2)
Gate tunneling currents
75(1)
Bulk current
76(1)
Semiconductor charges
77(2)
Drain-and source-associated inversion charges
79(2)
Summary of n-channel MOSFET equations: UCCM, current, charges, transconductances, and capacitances including short-channel effects
81(1)
An alternative low-frequency small-signal model of the MOSFET in saturation
81(3)
Problems
84(2)
References
86(2)
CMOS technology, components, and layout techniques
88(46)
An overview of CMOS technology
88(5)
Basic process steps in monolithic IC fabrication
88(1)
Generic deep-submicron CMOS process flow
89(3)
Main parameters in 350-, 180-, and 90-nm processes
92(1)
Devices in CMOS technology
93(21)
Resistors
94(7)
Capacitors
101(8)
Inductors
109(3)
Bipolar transistors
112(2)
Latchup
114(1)
Analog layout issues
115(13)
Optical lithography
115(3)
Mask layout and design rules
118(3)
MOSFET layout
121(7)
Problems
128(2)
References
130(4)
Temporal and spatial fluctuations in MOSFETs
134(43)
Types of noise
134(3)
Thermal noise
134(2)
Shot noise
136(1)
Flicker noise
136(1)
Modeling the drain-current fluctuations in MOSFETs
137(2)
Thermal noise in MOSFETs
139(5)
Channel thermal noise
139(1)
Short-channel effects on channel thermal noise
140(1)
Induced gate noise
141(3)
Flicker noise in MOSFETs
144(3)
Design-oriented noise models
147(7)
Consistency of noise models
147(1)
The thermal noise excess factor
147(1)
Flicker noise in terms of inversion levels
148(2)
The corner frequency
150(1)
Two-port noise models
151(3)
Systematic and random mismatch
154(16)
Pelgrom's model of mismatch
155(6)
(Mis)matching energy
161(1)
The number-fluctuation mismatch model
162(2)
The dependence of mismatch on bias, dimensions, and technology
164(3)
Matching analysis of analog circuits
167(3)
Problems
170(5)
References
175(2)
Current mirrors
177(22)
A simple MOS current mirror
177(10)
The ideal current mirror
177(1)
The two-transistor current mirror
177(2)
Error caused by difference between drain voltages
179(1)
Error caused by transistor mismatch
180(4)
Small-signal characterization and frequency response
184(2)
Noise
186(1)
Cascode current mirrors
187(4)
Self-biased cascode current mirrors
188(1)
High-swing cascode current mirrors
189(2)
Advanced current mirrors
191(1)
Class-AB current mirrors
192(1)
Harmonic distortion
193(2)
Problems
195(3)
References
198(1)
Current sources and voltage references
199(26)
A simple MOS current source
199(1)
The Widlar current source
200(1)
Self-biased current sources (SBCSs)
201(4)
A MOSFET-only self-biased current source
205(3)
Bandgap voltage references
208(9)
The operating principle of the bandgap reference
209(1)
CMOS bandgap references
210(4)
A CMOS bandgap reference with sub-1-V operation
214(2)
A resistorless CMOS bandgap reference
216(1)
CMOS voltage references based on weighted VGS
217(1)
A current-calibrated CMOS PTAT voltage reference
218(1)
Problems
219(3)
References
222(3)
Basic gain stages
225(67)
Common-source amplifiers
225(14)
Resistive load
225(1)
Diode-connected load
226(2)
The intrinsic gain stage
228(3)
Current source load
231(5)
The push-pull amplifier (static CMOS inverter)
236(3)
Common-gate amplifiers
239(3)
Source followers
242(4)
Cascode amplifiers
246(6)
Telescopic-and folded-cascode amplifiers
246(4)
The gain-boost technique
250(2)
Differential amplifiers
252(26)
The source-coupled pair
252(7)
Resistive-load differential amplifiers
259(1)
Current-mirror-load differential amplifiers
260(18)
Sizing and biasing of MOS transistors for amplifier design
278(5)
Sizing and biasing of a common-source amplifier
279(1)
The design procedure for a common-source amplifier
280(1)
MOSVIEW: a graphical interface for MOS transistor design
281(2)
Reuse of MOS analog design
283(5)
Effects of scaling on analog circuits
284(1)
Analog resizing rules
285(3)
Problems
288(2)
References
290(2)
Operational amplifiers
292(74)
Applications and performance paramcters
292(7)
The ideal operational amplifier
292(1)
Basic applications of operational amplifiers
293(4)
Performance parameters
297(2)
The differential amplifier as an operational amplifier
299(3)
The simple-stage differential amplifier
299(2)
The telescopic-cascode differential amplifier
301(1)
The symmetric operational amplifier
302(4)
DC characteristics
302(2)
Small-signal characteristics and noise
304(1)
Slew rate
305(1)
The folded-cascode operational amplifiers
306(14)
DC characteristics
306(2)
Small-signal characteristics and noise
308(4)
Slew rate
312(8)
Two-stage operational amplifiers
320(19)
Cascade versus cascode amplifiers
320(1)
DC characteristics of the two-stage amplifier
321(1)
Small-signal characteristics of the two-stage Miller-compensated op amp
322(12)
Slew rate
334(2)
Alternative forms of compensation of the two-stage op amp
336(3)
Three-stage operational amplifiers
339(1)
Rail-to-rail input stages
340(2)
Class-AB output stages for operational amplifiers
342(8)
Fully-differential operational amplifiers
350(9)
Systematic offset of a two-stage op amp
359(1)
Problems
360(3)
References
363(3)
Fundamentals of integrated continuous-time filters
366(38)
Basics of MOSFET-C filters
366(12)
The MOSFET as a tunable resistor
367(1)
Balanced transconductors for MOSFET-C filters
368(2)
MOSFET-C integrators
370(6)
Filter examples
376(2)
Basics of OTA-C filters
378(15)
Transconductors
379(4)
Gm-C integrators
383(3)
Signal-to-noise ratio, dynamic range, and power
386(4)
Filter examples
390(3)
Digitally-programmable continuous-time filters
393(2)
On-chip tuning schemes
395(2)
Distortion of the MOSFET operating as a resistor
397(2)
Problems
399(1)
References
400(4)
Fundamentals of sampled-data circuits
404(48)
MOS sample-and-hold circuits
404(19)
Sample-and-hold basics
404(2)
Thermal noise
406(3)
Switch on-resistance
409(1)
Sampling distortion due to switch on-resistance
410(2)
Linearization of the MOS sampling switch
412(1)
Charge injection by the switch
413(4)
Low-voltage sample-and-hold circuits
417(4)
Jitter analysis
421(1)
Tradeoff between resolution and sampling rate in analog-to-digital converters
422(1)
Basics of switched-capacitor filters
423(14)
Basic principles of operation of switched-capacitor circuits
423(3)
Switched-capacitor integrators
426(3)
Offset compensation
429(1)
Biquad filters
430(3)
Amplifier specifications
433(2)
Low-distortion switched-capacitor filters
435(2)
Switched-capacitor circurits as charge processors
437(4)
Realization of linear voltage processors
438(2)
Implementation issues
440(1)
Alternative switched-circuit techniques
441(3)
Modeling the sampling distortion due to the non-linearity of the switch on-resistance
444(2)
Problems
446(4)
References
450(2)
Overview of MOSFET models and parameter extraction for design
452(31)
MOSFET models for circuit simulation
452(8)
Threshold-voltage-based models (BSIM3 and BSIM4)
453(1)
Surface-potential-based models (HiSIM, MM11, and PSP)
454(4)
Charge-based models (EKV, ACM, and BSIM5)
458(2)
Parameter extraction for first-order design
460(7)
Specific current and threshold voltage
461(2)
The slope factor
463(2)
Mobility
465(2)
Comparison between experiment and the ACM model in a 0.35-μm technology
467(3)
Comparison between simulation and the ACM model in a 0.13-μm technology
470(3)
The Early voltage
473(6)
Problems
479(1)
References
480(3)
Index 483
Márcio Cherem Schneider is a Professor in the Electrical Engineering Department at the Federal University of Santa Catarina, Brazil, where he has worked since 1976. He has also spent a year at the Swiss Federal Institute of Technology (EPFL) and has worked as a Visiting Associate Professor in the Department of Electrical and Computer Engineering at Texas A&M University. His current research interests mainly focus on MOSFET modeling and transistor-level design, in particular of analog and RF circuits. Carlos Galup-Montoro is currently a Visiting Scholar in the Electrical Engineering Department at the University of California, Berkeley, and a Professor in the Electrical Engineering Department at the Federal University of Santa Catarina, Brazil, where he has worked since 1990. His main research interests are in field-effect transistor modeling and transistor-level design.