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E-raamat: CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test

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CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and TestSuurem pilt
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The monograph will be dedicated to SRAM (memory) design and test issues in nano-scaled technologies by adapting the cell design and chip design considerations to the growing process variations with associated test issues. Purpose: provide process-aware solutions for SRAM design and test challenges.



This book covers a broad range of topics related to SRAM design and testing. It includes everything from SRAM operation basics through cell electrical and physical design to process-aware and economical approach to SRAM testing.

1 Introduction and Motivation 1
1.1 Motivation
1
1.2 SRAM in the Computer Memory Hierarchy
3
1.3 Technology Scaling and SRAM Design and Test
4
1.3.1 Moore's Law
5
1.3.2 Obstacles in SRAM Scaling
6
1.4 SRAM Test Economics
7
1.5 SRAM Design and Test Tradeoffs
8
1.5.1 Area and Stability
9
1.5.2 Quality and Yield
9
1.5.3 Test Coverage and Test Time
10
1.6 Redundancy
11
2 SRAM Circuit Design and Operation 13
2.1 Introduction
13
2.2 SRAM Block Structure
13
2.3 SRAM Cell Design
15
2.3.1 Four-Transistor (4T) SRAM Cell with Polysilicon Resistor Load
15
2.3.2 Six-Transistor (6T) CMOS SRAM Cell
16
2.3.2.1 Read Operation
17
2.3.2.2 Write Operation
19
2.3.3 Four-Transistor (4T) Loadless SRAM Cell
21
2.4 Cell Layout Considerations
22
2.5 Sense Amplifier and Bit Line Precharge-Equalization
26
2.6 Write Driver
30
2.7 Row Address Decoder and Column MUX
31
2.8 Address Transition Detector
33
2.9 Timing Control Schemes
34
2.9.1 Delay-Line Based Timing Control
35
2.9.2 Replica-Loop Based Timing Control
35
2.9.3 Pipelined Timing Control
38
2.10 Summary
38
3 SRAM Cell Stability: Definition, Modeling and Testing 39
3.1 Introduction
39
3.2 Static Noise Margin of SRAM Cells
40
3.3 SNM Definitions
41
3.3.1 Inverter V,L, V/H, VOL and VOH
41
3.3.2 Noise Margins NMH and NML with VOL and VOH Defined as Stable Logic Points
42
3.3.3 Noise Margins NMH and NML with VOL and VOH Defined as —1 Slope Points
42
3.3.4 SNM as a Side of the Maximum Square Drawn Between the Inverter Characteristics
44
3.4 Analytical Expressions for SNM Calculation
46
3.4.1 Analytical SNM Expression for a 4T SRAM Cell with Polysilicon Resistor Load
47
3.4.2 Analytical SNM Expression for a 6T SRAM Cell
49
3.4.3 Conclusions from SNM Analytical Expressions
51
3.4.4 Analytical SNM Expression for a Loadless 4T SRAM Cell
51
3.4.4.1 Alpha-Power Law Model
51
3.4.4.2 Analytical SNM Expression Derivation
53
3.4.4.3 Finding VOH and VIL
53
3.4.4.4 Finding VOL and VIH
54
3.4.4.5 SNM Expression for 4T Loadless SRAM Cell
55
3.4.4.6 Simulation Results vs. the Analytical Expression
56
3.5 SRAM Cell Stability Sensitivity Factors
58
3.5.1 SRAM SNM and Process Parameter Variations
59
3.5.2 SRAM SNM and Non-catastrophic Defects
62
3.5.2.1 SNM vs. Non-catastrophic Breaks and Bridges
62
3.5.3 SRAM SNM and Operating Voltages Variation
64
3.6 SRAM Cell Stability Fault Model
68
3.7 SRAM Cell Stability Detection Concept
69
3.8 March Tests and Stability Fault Detection in SRAMs
72
3.8.1 March 11N
72
3.8.2 Hammer Test
73
3.8.3 Coupling Fault Detection
74
3.9 Summary
77
4 Traditional SRAM Fault Models and Test Practices 79
4.1 Introduction
79
4.2 Traditional Fault Models
80
4.3 Traditional SRAM Test Practices
85
4.3.1 March Tests
87
4.3.1.1 March C
91
4.3.1.2 March C-
91
4.3.1.3 Hammer Test
91
4.3.2 Parametric Testing
92
4.3.2.1 Burn-In Test (BI)
93
4.3.2.2 IDDQ Test
97
4.3.2.3 Limitations of /Div Testing in Scaled Technologies
98
4.3.3 Design For Test Techniques
99
4.3.3.1 Built-In Self Test
100
4.4 Summary
101
5 Techniques for Detection of SRAM Cells with Stability Faults 103
5.1 Introduction
103
5.2 Classification of SRAM Cell Stability Test Techniques
103
5.3 Passive SRAM Cell Stability Test Techniques
104
5.3.1 Data Retention Test
104
5.3.2 Low-Voltage Test
108
5.4 Active SRAM Cell Stability Test Techniques
111
5.4.1 Active Techniques with a Single Test Stress Level
112
5.4.1.1 Soft Defect Detection
112
5.4.1.2 Weak Write Test Mode
114
5.4.1.3 Integrated Weak Write Test Mode
118
5.4.1.4 Word Line Driver Underdrive During a Write Operation
119
5.4.1.5 Soft Defect Detection-II (SDD-II) Technique
120
5.4.1.6 No Write Recovery Test Mode
123
5.4.1.7 Word Line Voltage Overdrive During a Read Operation
125
5.4.2 Active Techniques with Programmable Test Stress Levels
126
5.4.2.1 Short Write Test Mode
127
5.4.2.2 Programmable Weak Write Test Mode
130
5.4.2.3 Programmable Integrated Weak Write Test Mode
131
5.4.2.4 Programmable Read Current Ratio Technique with a Pass Transistor Technique
135
5.4.2.5 Programmable Read Current Ratio Technique with Floating Bit Lines
141
5.4.2.6 Programmable Word Line Pulsing Technique
147
5.5 Summary
156
6 Soft Errors in SRAMs: Sources, Mechanisms and Mitigation Techniques 159
6.1 Introduction
159
6.2 Soft Error Mechanism
161
6.3 Sources of Soft Errors
163
6.3.1 Alpha Particles
163
6.3.2 Neutron-Induced '0B Fission
164
6.3.3 High-Energy Cosmic Rays
165
6.4 Soft Errors and Defects in the Pull-Up Path of a Cell
166
6.5 Soft Error Mitigation Techniques
167
6.5.1 Error Detection and Correction
167
6.5.1.1 Parity Check
168
6.5.1.2 Error Correction Codes
168
6.5.1.3 Circuit and/or System Redundancy
174
6.5.2 Removing Radiation Sources or Reducing Their Intensity
175
6.5.3 Increasing the Capacitance of the Storage Nodes
176
6.5.4 Inserting Resistors in the Feedback Loop of an SRAM Cell
177
6.6 Leakage-Reduction Techniques and the SER
179
6.7 Summary
180
References 183
Index 191
Prof. Sachdev has authored several successful books with Springer
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