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E-raamat: Comparators in Nanometer CMOS Technology

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Comparators in Nanometer CMOS TechnologySuurem pilt
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This book covers the complete spectrum of the fundamentals of clocked, regenerative comparators, their state-of-the-art, advanced CMOS technologies, innovative comparators inclusive circuit aspects, their characterization and properties. Starting from the basics of comparators and the transistor characteristics in nanometer CMOS, seven high-performance comparators developed by the authors in 120nm and 65nm CMOS are described extensively. Methods and measurement circuits for the characterization of advanced comparators are introduced. A synthesis of the largely differing aspects of demands on modern comparators and the properties of devices being available in nanometer CMOS, which are posed by the so-called nanometer hell of physics, is accomplished. The book summarizes the state of the art in integrated comparators. Advanced measurement circuits for characterization will be introduced as well as the method of characterization by bit-error analysis usually being used for characterization of optical receivers. The book is compact, and the graphical quality of the illustrations is outstanding. This book is written for engineers and researchers in industry as well as scientists and Ph.D students at universities. It is also recommendable to graduate students specializing on nanoelectronics and microelectronics or circuit design.
1 Introduction
1(10)
1.1 Motivation
1(1)
1.2 Classification of Comparators
2(9)
1.2.1 Comparators for Comparing Analog Values
3(5)
1.2.2 Comparators for Comparing Digital Values
8(1)
References
9(2)
2 Fundamentals of Clocked, Regenerative Comparators
11(38)
2.1 The Static Latch
11(3)
2.2 Basic Clocked, Regenerative Comparator Circuits
14(5)
2.3 Analog MOS Switches
19(4)
2.3.1 Analog Switch Implementation
20(1)
2.3.2 Charge Injection and Clock Feedthrough
21(2)
2.4 Characterization of Comparators
23(14)
2.4.1 Noise, Offset and Hysteresis
23(8)
2.4.2 Sensitivity, Metastability Error and Bit Error
31(6)
2.4.3 Delay Time, Overdrive Recovery Time
37(1)
2.4.4 Power Consumption
37(1)
2.5 Measurement Techniques of Clocked, Regenerative Comparators from the Literature
37(3)
2.6 A Low Level Consideration of the Delay Time Mismatch for Two Inverters
40(9)
References
46(3)
3 State of the Art
49(16)
References
62(3)
4 Nanometer CMOS Technology
65(14)
4.1 120 nm CMOS Technology
65(5)
4.2 65 nm Low-Power CMOS Technology
70(5)
4.2.1 Transistor Characteristics
71(4)
4.3 Consequences of Device Properties on Circuit Design
75(4)
4.3.1 Transistor Speed and Gain
75(1)
4.3.2 Supply Voltage and Signal Headroom
75(1)
4.3.3 Low-Frequency Noise
75(1)
4.3.4 Matching
76(1)
4.3.5 Gate Leakage Current
76(1)
4.3.6 Linearity
76(1)
References
77(2)
5 Measurement Circuits and Setup
79(72)
5.1 A 10 GHz Voltage Buffer in 0.12 μm CMOS Technology
79(15)
5.1.1 Circuit Description
80(6)
5.1.2 Measurement Results
86(3)
5.1.3 Redesign of the Voltage Buffer for Usage in a Test Chip with a Comparator
89(5)
5.2 Temperature Measurement
94(5)
5.3 Transfer Stage and Delay Time Measurement of the Comparator
99(16)
5.4 Clock Driver with Voltage-Controlled Delay Lines and a Reference Output
115(16)
5.5 Measurement Setup
131(3)
5.6 Microcontroller Board
134(17)
References
149(2)
6 Comparators in 120 nm CMOS
151(64)
6.1 A 660 μW, 1.5 GHz Comparator in 120 nm CMOS
151(8)
6.1.1 Circuit Description
151(4)
6.1.2 Measurement Results
155(4)
6.2 A 360 μW, 2 GHz Comparator in 120 nm CMOS with Delayed Reset
159(11)
6.2.1 Circuit Description
159(7)
6.2.2 Measurement Results
166(4)
6.3 A 812 μW, 4 GHz Comparator in 120 nm CMOS with Adjustable Sensitivity
170(13)
6.3.1 Circuit Description
170(8)
6.3.2 Measurement Results
178(5)
6.4 A Comparator in 120 nm CMOS Requiring 0.5 V and 18 μW at 600 MHz Clock
183(13)
6.4.1 Circuit Description
184(8)
6.4.2 Measurement Results
192(4)
6.5 A Comparator in 120 nm CMOS with Advanced Sensitivity Tuning
196(19)
6.5.1 Circuit Description
196(9)
6.5.2 Measurement Results
205(5)
6.5.3 Short Extension to Reduce the Influence of Noise and Mismatch
210(3)
References
213(2)
7 Comparators in 65 nm CMOS
215(24)
7.1 A 7 GHz Comparator
215(12)
7.1.1 Circuit Description
215(6)
7.1.2 Measurement Results
221(6)
7.2 A Low-Offset Comparator
227(12)
7.2.1 Circuit Description
227(6)
7.2.2 Measurement Results
233(4)
References
237(2)
8 Conclusion and Comparison
239(8)
References
244(3)
Index 247
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