Introduction |
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xv | |
Acknowledgments |
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xix | |
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Introduction to PCB Design and CAD |
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1 | (16) |
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Computer-Aided Design and the OrCAD Design Suite |
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1 | (1) |
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Printed Circuit Board Fabrication |
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2 | (9) |
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PCB cores and layer stack-up |
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2 | (2) |
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4 | (1) |
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Photolithography and chemical etching |
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5 | (3) |
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8 | (1) |
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9 | (2) |
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Function of OrCAD Layout in the PCB Design Process |
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11 | (3) |
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Design Files Created by Layout |
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14 | (3) |
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Layout format files (.MAX) |
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14 | (1) |
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Postprocess (Gerber) files |
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14 | (1) |
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PCB assembly layers and files |
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14 | (3) |
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Introduction to the PCB Design Flow by Example |
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17 | (22) |
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Overview of the Design Flow |
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17 | (1) |
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Creating a Circuit Design with Capture |
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17 | (8) |
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17 | (3) |
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20 | (3) |
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Wiring (connecting) the parts |
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23 | (1) |
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Creating the Layout netlist in Capture |
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23 | (2) |
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Designing the PCB with Layout |
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25 | (14) |
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Starting Layout and importing the netlist |
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25 | (4) |
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29 | (2) |
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31 | (1) |
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32 | (1) |
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32 | (2) |
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34 | (1) |
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34 | (1) |
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Performing a design rule check |
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35 | (1) |
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Postprocessing the board design for manufacturing |
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35 | (4) |
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Project Structures and the Layout Tool Set |
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39 | (26) |
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Project Setup and Schematic Entry Details |
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39 | (4) |
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Capture projects explained |
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39 | (3) |
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Capture part libraries explained |
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42 | (1) |
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Understanding the Layout Environment and Tool Set |
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43 | (22) |
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43 | (1) |
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44 | (2) |
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The session frame and Design window |
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46 | (1) |
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47 | (10) |
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Controlling the autorouter |
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57 | (3) |
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Postprocessing and layer details |
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60 | (5) |
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Introduction to Industry Standards |
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65 | (14) |
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Introduction to the Standards Organizations |
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66 | (2) |
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Institute for Printed Circuits (IPC-Association Connecting Electronics Industries) |
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66 | (1) |
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Electronic Industries Alliance (EIA) |
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66 | (1) |
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Joint Electron Device Engineering Council (JEDEC) |
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66 | (1) |
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International Engineering Consortium (IEC) |
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67 | (1) |
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67 | (1) |
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American National Standards Institute (ANSI) |
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67 | (1) |
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Institute of Electrical and Electronics Engineers (IEEE) |
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67 | (1) |
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Classes and Types of PCBs |
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68 | (2) |
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68 | (1) |
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68 | (1) |
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Fabrication types and assembly subclasses |
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69 | (1) |
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OrCAD Layout design complexity levels---IPC performance classes |
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69 | (1) |
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IPC land pattern density levels |
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70 | (1) |
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Introduction to Standard Fabrication Allowances |
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70 | (1) |
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70 | (1) |
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Breakout and annular ring control |
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70 | (1) |
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PCB Dimensions and Tolerances |
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71 | (4) |
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71 | (1) |
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Tooling area allowances and effective panel usage |
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72 | (1) |
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Standard finished PCB thickness |
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72 | (1) |
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73 | (1) |
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73 | (1) |
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Copper thickness for PTHs and vias |
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73 | (1) |
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Copper cladding/foil thickness |
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74 | (1) |
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Copper Trace and Etching Tolerances |
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75 | (1) |
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76 | (1) |
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77 | (1) |
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77 | (2) |
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77 | (1) |
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77 | (2) |
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Introduction to Design for Manufacturing |
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79 | (30) |
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Introduction to PCB Assembly and Soldering Processes |
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79 | (1) |
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79 | (2) |
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Manual assembly processes |
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79 | (1) |
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Automated assembly processes (pick and place) |
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80 | (1) |
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81 | (4) |
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81 | (1) |
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82 | (2) |
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84 | (1) |
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Component Placement and Orientation Guide |
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85 | (1) |
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Component Spacing for Through-hole Devices |
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86 | (1) |
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86 | (1) |
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Integrated circuit through-hole devices |
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86 | (1) |
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Mixed discrete and IC through-hole devices |
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86 | (1) |
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86 | (1) |
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Component Spacing for Surface-Mounted Devices |
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86 | (1) |
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86 | (1) |
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86 | (1) |
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Mixed discrete and IC SMDs |
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86 | (1) |
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Mixed THD and SMD Spacing Requirements |
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86 | (8) |
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Footprint and Padstack Design for PCB Manufacturability |
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94 | (1) |
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Land Patterns for Surface-Mounted Devices |
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94 | (7) |
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96 | (3) |
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99 | (2) |
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Land Patterns for Through-hole Devices |
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101 | (8) |
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Footprint design for through-hole devices |
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101 | (2) |
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Padstack design for through-hole devices |
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103 | (1) |
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103 | (1) |
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PTH land dimension (annular ring width) |
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104 | (2) |
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Clearance between plane layers and PTHs |
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106 | (1) |
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Soldermask and solder paste dimensions |
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107 | (2) |
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PCB Design for Signal Integrity |
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109 | (58) |
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Circuit Design Issues Not Related to PCB Layout |
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109 | (10) |
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109 | (1) |
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110 | (1) |
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111 | (1) |
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Issues Related to PBCLayout |
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111 | (1) |
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Electromagnetic Interference and Cross Talk |
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111 | (1) |
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Magnetic fields and inductive coupling |
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112 | (3) |
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115 | (2) |
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Electric fields and capacitive coupling |
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117 | (2) |
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Ground Planes and Ground Bounce |
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119 | (8) |
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What ground is and what it is not |
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119 | (3) |
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122 | (1) |
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Ground bounce and rail collapse |
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123 | (2) |
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Split power and ground planes |
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125 | (2) |
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PCB Electrical Characteristics |
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127 | (17) |
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127 | (6) |
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133 | (4) |
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137 | (2) |
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139 | (3) |
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142 | (1) |
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Transmission line terminations |
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143 | (1) |
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144 | (23) |
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Parts placement for electrical considerations |
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145 | (1) |
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146 | (5) |
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Bypass capacitors and fanout |
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151 | (1) |
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Trace width for current carrying capability |
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151 | (2) |
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Trace width for controlled impedance |
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153 | (10) |
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Trace spacing for voltage withstanding |
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163 | (1) |
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Trace spacing to minimize cross talk (3w rule) |
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163 | (1) |
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Traces with acute and 90° angles |
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164 | (3) |
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Making and Editing Capture Parts |
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167 | (44) |
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The Capture Part Libraries |
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167 | (1) |
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168 | (1) |
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168 | (1) |
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169 | (1) |
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169 | (1) |
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170 | (1) |
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The Select tool and settings |
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170 | (1) |
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170 | (1) |
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171 | (1) |
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171 | (1) |
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Constructing Capture Parts |
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171 | (1) |
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Method 1: Constructing Parts Using the New Part Option (Design Menu) |
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172 | (15) |
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Design example for a passive, homogeneous part |
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172 | (8) |
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Design example for an active, multipart, homogeneous component |
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180 | (3) |
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Assigning power pin visibility |
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183 | (1) |
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Design example for a passive, heterogeneous part |
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184 | (3) |
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Method 2: Constructing Parts with Capture Using the Design Spreadsheet |
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187 | (3) |
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Method 3: Constructing Parts Using Generate Part from the Tools Menu |
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190 | (2) |
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Method 4: Generating Parts with the PSpice Model Editor |
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192 | (16) |
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Generating a Capture part library from a PSpice model library |
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193 | (1) |
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Making and/or Obtaining PSpice Libraries for Making New Capture Parts |
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194 | (1) |
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Downloading libraries and/or models from the Internet |
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195 | (1) |
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Making a PSpice model from a Capture project |
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196 | (10) |
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Adding PSpice templates (models) to preexisting Capture parts |
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206 | (2) |
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Constructing Capture Symbols |
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208 | (3) |
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Making and Editing Layout Footprints |
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211 | (52) |
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Introduction to the Library Manager |
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211 | (6) |
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Introduction to Layout's Footprint Libraries and Naming Conventions |
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212 | (1) |
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Layout's footprint libraries |
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213 | (1) |
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213 | (4) |
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The Composition of Footprints |
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217 | (4) |
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217 | (1) |
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218 | (2) |
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220 | (1) |
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Datums and insertion origins |
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220 | (1) |
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The Basic Footprint Design Process |
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221 | (5) |
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226 | (5) |
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Accessing existing padstacks |
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227 | (1) |
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Editing padstack properties from the spreadsheet |
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228 | (1) |
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Saving footprints and padstacks |
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229 | (2) |
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Footprint Design Examples |
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231 | (12) |
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Design Example 1: a surface-mount footprint design |
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232 | (5) |
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Design Example 2: a modified through-hole footprint design |
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237 | (6) |
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Using the Pad Array Generator |
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243 | (20) |
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243 | (1) |
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Footprint design for PGAs |
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243 | (5) |
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Footprint design for BGAs |
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248 | (10) |
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Blind, buried, and microvias |
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258 | (1) |
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259 | (2) |
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Printing a catalog of a footprint library |
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261 | (2) |
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263 | (148) |
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Overview of the Design Flow |
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264 | (2) |
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Example 1: Dual Power Supply, Analog Design |
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266 | (56) |
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Initial design concept and preparation |
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267 | (1) |
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Project setup and design in Capture |
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268 | (17) |
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Defining the board requirements |
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285 | (3) |
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Importing the design into Layout |
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288 | (1) |
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289 | (17) |
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306 | (10) |
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316 | (2) |
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318 | (4) |
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Example 2: Mixed Analog/Digital Design Using Split Power, Ground Planes |
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322 | (30) |
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Mixed-signal circuit design in Capture |
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322 | (2) |
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Power and ground connections to digital and analog parts |
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324 | (1) |
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Connecting separate analog and digital grounds to a split plane |
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324 | (3) |
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Using busses for digital nets |
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327 | (1) |
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Defining the layer stack-up for split planes |
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328 | (2) |
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Establishing a primary power plane |
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330 | (4) |
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Creating split ground planes |
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334 | (2) |
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Creating nested power planes with copper pours |
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336 | (2) |
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Using anti-copper on plane layers |
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338 | (2) |
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Setting up and running the autorouter |
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340 | (2) |
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Moving a routed trace to a different layer |
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342 | (1) |
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Adding ground planes and guard traces to routing layers |
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342 | (3) |
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Defining vias for flood planes/pours |
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345 | (2) |
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Setting the copper pour spacing |
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347 | (1) |
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Stitching a ground plane manually |
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348 | (1) |
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Using anti-copper obstacles on copper pours |
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349 | (1) |
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Routing guard traces and rings |
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349 | (3) |
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Example 3: Multipage, Multipower, and Multiground Mixed A/D PCB Design with PSpice |
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352 | (24) |
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Project setup for PSpice simulation and Layout |
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354 | (2) |
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Adding schematic pages to the design |
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356 | (2) |
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Using off-page connectors with wires |
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358 | (1) |
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Using off-page connectors with busses |
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359 | (1) |
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Setting up multiple-ground systems |
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359 | (1) |
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Setting up PSpice sources |
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360 | (1) |
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Performing PSpice simulations |
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361 | (3) |
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Preparing the simulated project for Layout |
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364 | (1) |
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Assigning a new technology file |
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365 | (1) |
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Placing parts on the bottom (back) of a board |
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365 | (1) |
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Layer stack-up for a multiground system |
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365 | (2) |
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367 | (1) |
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Through-hole and blind via setup |
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367 | (1) |
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Fanning out a board with multiple vias |
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367 | (3) |
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Overriding known errors in Layout |
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370 | (1) |
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Autorouting with the DRC/route box |
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370 | (2) |
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Using forced thermals to connect ground planes |
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372 | (1) |
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Using the AutoECO to update a board from Capture |
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372 | (4) |
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Example 4: High-Speed Digital Design |
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376 | (21) |
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Layer setup for microstrip transmission lines |
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380 | (1) |
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Via design for heat spreaders |
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381 | (1) |
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Constructing a heat spreader with copper area obstacles |
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382 | (1) |
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Using free vias as heat pipes |
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382 | (5) |
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Determining critical trace length of transmission lines |
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387 | (1) |
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Routing controlled impedance traces |
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388 | (2) |
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Moated ground areas for clock circuits |
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390 | (1) |
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390 | (2) |
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392 | (3) |
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Stitching a ground plane with the free via matrix |
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395 | (2) |
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397 | (7) |
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397 | (1) |
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Design cache---cleanup, replace, update |
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398 | (2) |
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400 | (1) |
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401 | (2) |
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Making a custom Capture template |
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403 | (1) |
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Making a custom Layout technology/template file |
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403 | (1) |
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404 | (7) |
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Using the Stackup Editor with an active board design |
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404 | (3) |
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Using the Stackup Editor to set up a custom technology or template file |
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407 | (1) |
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Submitting stack-up drawings with Gerber files |
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408 | (1) |
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408 | (1) |
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Printing a footprint catalog from a PCB design |
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409 | (2) |
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Postprocessing and Board Fabrication |
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411 | (12) |
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The Circuit Design with OrCAD |
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411 | (6) |
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Schematic design in Capture |
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411 | (2) |
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The board design with Layout |
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413 | (1) |
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Postprocessing the design with Layout |
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414 | (3) |
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417 | (6) |
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417 | (1) |
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Setting up a user account |
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417 | (1) |
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Submitting Gerber files and requesting a quote |
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418 | (1) |
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Annotating the layer types and stack-up |
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419 | (3) |
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Receipt inspection and testing |
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422 | (1) |
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422 | (1) |
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423 | (68) |
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Using PSpice to Simulate Transmission Lines |
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423 | (4) |
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Simulating digital transmission lines |
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424 | (3) |
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Simulating analog signals |
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427 | (1) |
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Using Microsoft Excel with a Bill of Materials Generated by Capture |
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427 | (2) |
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Using the Specctra Autorouter with Layout |
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429 | (8) |
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437 | (12) |
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Opening a Layout-generated Gerber file with GerbTool |
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437 | (1) |
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Making a .DRL file for a CNC machine |
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438 | (5) |
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443 | (6) |
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Using the IPC-7351 Land Pattern Viewer |
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449 | (3) |
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Using CAD Tools to 3-D Model a PCB |
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452 | (3) |
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Appendix A: Layout Technology Files |
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455 | (2) |
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Appendix B: List of Design Standards |
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457 | (2) |
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Appendix C: A Partial List of Packages and Footprints and Some of the Footprints Included in OrCAD Layout |
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459 | (12) |
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Appendix D: Rise and Fall Times for Various Logic Families |
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471 | (2) |
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Appendix E: Drill and Screw Dimensions |
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473 | (2) |
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Appendix F: References by Subject |
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475 | (16) |
Bibliography and References |
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491 | (4) |
Index |
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495 | |