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E-raamat: Computer Architecture: A Quantitative Approach

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(Departments of Electrical Engineering and Computer Science, Stanford University, USA), (Pardee Professor of Computer Science, Emeritus, University of California at Berkeley, USA)
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Fully updated to account for emerging technologies, this comprehensive work on computer architecture explores cutting edge technologies in computer design and is intended for advanced undergraduate and graduate students in hardware engineering as well as professionals interested in state of the art developments. Beginning with an overview of principles of quantitative design and analysis, the work covers topics such as memory hierarchies, instruction, data and thread level parallelism, large scale computing for cloud and distributive computing tasks, pipelining, and GPU based parallel processing. Chapters include numerous technical illustrations, tables, and code samples as well as case studies and practice exercises. Patterson is the chair of computer science at the University of California, Berkeley and Hennessy is the president of Stanford University. Annotation ©2011 Book News, Inc., Portland, OR (booknews.com)

The computing world today is in the middle of a revolution: mobile clients and cloud computing have emerged as the dominant paradigms driving programming and hardware innovation today. The Fifth Edition of Computer Architecture focuses on this dramatic shift, exploring the ways in which software and technology in the cloud are accessed by cell phones, tablets, laptops, and other mobile computing devices. Each chapter includes two real-world examples, one mobile and one datacenter, to illustrate this revolutionary change.

  • Updated to cover the mobile computing revolution
  • Emphasizes the two most important topics in architecture today: memory hierarchy and parallelism in all its forms.
  • Develops common themes throughout each chapter: power, performance, cost, dependability, protection, programming models, and emerging trends ("What's Next")
  • Includes three review appendices in the printed text. Additional reference appendices are available online.
  • Includes updated Case Studies and completely new exercises.


The computing world today is in the middle of a revolution: mobile clients and cloud computing have emerged as the dominant paradigms driving programming and hardware innovation today. The Fifth Edition of Computer Architecture focuses on this dramatic shift, exploring the ways in which software and technology in the cloud are accessed by cell phones, tablets, laptops, and other mobile computing devices. Each chapter includes two real-world examples, one mobile and one datacenter, to illustrate this revolutionary change.

  • Part of Intel's 2012 Recommended Reading List for Developers
  • Updated to cover the mobile computing revolution
  • Emphasizes the two most important topics in architecture today: memory hierarchy and parallelism in all its forms.
  • Develops common themes throughout each chapter: power, performance, cost, dependability, protection, programming models, and emerging trends ("What's Next")
  • Includes three review appendices in the printed text. Additional reference appendices are available online.
  • Includes updated Case Studies and completely new exercises.

Arvustused

"What has made this book an enduring classic is that each edition is not an update, but an extensive revision that presents the most current information and unparalleled insight into this fascinating and fast changing field. For me, after over twenty years in this profession, it is also another opportunity to experience that student-grade admiration for two remarkable teachers." --From the Foreword by Luiz André Barroso, Google, Inc.

"This is an academic textbook that is also suitable for a far broader readership. Each chapter is organised in the same structure, with the main content supported by case studies and exercises Having read this book I now have a far better understanding of why processors from all the different designers and manufacturers are so different. Memory hierarchies, multicore architectures and compiler optimisation are all covered in great detail. I was particularly interested in their discussion of graphical processing units and how they are suitable for far more than just graphical workloads What is great about this book is that it moves with the times. There is a lot of content on processors for mobile computing, and power usage is a pervasive theme. At the other extreme there is an excellent chapter on warehouse scale computers, which offers tremendous insight into the cloud computing infrastructure provided by Google, Amazon and others. If your job has anything to do with IT infrastructure then I recommend this book as a must-read. As an academic text book it has both depth and breadth. And if you're just interested in the topic you'll gain a huge amount of insight into the fundamentals of computer architecture." --The Chartered Institute for IT

Muu info

Fully updated fifth edition covers the twin shifts to mobile and cloud computing, with new material, exercises, and case studies.
Foreword ix
Preface xv
Acknowledgments xxiii
Chapter 1 Fundamentals of Quantitative Design and Analysis
1.1 Introduction
2(3)
1.2 Classes of Computers
5(6)
1.3 Defining Computer Architecture
11(6)
1.4 Trends in Technology
17(4)
1.5 Trends in Power and Energy in Integrated Circuits
21(6)
1.6 Trends in Cost
27(6)
1.7 Dependability
33(3)
1.8 Measuring, Reporting, and Summarizing Performance
36(8)
1.9 Quantitative Principles of Computer Design
44(8)
1.10 Putting It All Together: Performance, Price, and Power
52(3)
1.11 Fallacies and Pitfalls
55(4)
1.12 Concluding Remarks
59(2)
1.13 Historical Perspectives and References
61(11)
Case Studies and Exercises by Diana Franklin
61(11)
Chapter 2 Memory Hierarchy Design
2.1 Introduction
72(6)
2.2 Ten Advanced Optimizations of Cache Performance
78(18)
2.3 Memory Technology and Optimizations
96(9)
2.4 Protection: Virtual Memory and Virtual Machines
105(7)
2.5 Crosscutting Issues: The Design of Memory Hierarchies
112(1)
2.6 Putting It All Together: Memory Hierachies in the ARM Cortex-A8 and Intel Core i7
113(12)
2.7 Fallacies and Pitfalls
125(4)
2.8 Concluding Remarks: Looking Ahead
129(2)
2.9 Historical Perspective and References
131(17)
Case Studies and Exercises by Norman P. Jouppi, Naveen Muralimanohar, and Sheng Li
131(17)
Chapter 3 Instruction-Level Parallelism and Its Exploitation
3.1 Instruction-Level Parallelism: Concepts and Challenges
148(8)
3.2 Basic Compiler Techniques for Exposing ILP
156(6)
3.3 Reducing Branch Costs with Advanced Branch Prediction
162(5)
3.4 Overcoming Data Hazards with Dynamic Scheduling
167(9)
3.5 Dynamic Scheduling: Examples and the Algorithm
176(7)
3.6 Hardware-Based Speculation
183(9)
3.7 Exploiting ILP Using Multiple Issue and Static Scheduling
192(5)
3.8 Exploiting ILP Using Dynamic Scheduling, Multiple Issue, and Speculation
197(5)
3.9 Advanced Techniques for Instruction Delivery and Speculation
202(11)
3.10 Studies of the Limitations of ILP
213(8)
3.11 Cross-Cutting Issues: ILP Approaches and the Memory System
221(2)
3.12 Multithreading: Exploiting Thread-Level Parallelism to Improve Uniprocessor Throughput
223(10)
3.13 Putting It All Together: The Intel Core i7 and ARM Cortex-A8
233(8)
3.14 Fallacies and Pitfalls
241(4)
3.15 Concluding Remarks: What's Ahead?
245(2)
3.16 Historical Perspective and References
247(15)
Case Studies and Exercises
247(15)
Jason D. Bakos
Robert P. Colwell
Chapter 4 Data-Level Parallelism in Vector, SIMD, and GPU Architectures
4.1 Introduction
262(2)
4.2 Vector Architecture
264(18)
4.3 SIMD Instruction Set Extensions for Multimedia
282(6)
4.4 Graphics Processing Units
288(27)
4.5 Detecting and Enhancing Loop-Level Parallelism
315(7)
4.6 Crosscutting Issues
322(1)
4.7 Putting It All Together: Mobile versus Server GPUs and Tesla versus Core i7
323(7)
4.8 Fallacies and Pitfalls
330(2)
4.9 Concluding Remarks
332(2)
4.10 Historical Perspective and References
334(10)
Case Study and Exercises
334(10)
Jason D. Bakos
Chapter 5 Thread-Level Parallelism
5.1 Introduction
344(7)
5.2 Centralized Shared-Memory Architectures
351(15)
5.3 Performance of Symmetric Shared-Memory Multiprocessors
366(12)
5.4 Distributed Shared-Memory and Directory-Based Coherence
378(8)
5.5 Synchronization: The Basics
386(6)
5.6 Models of Memory Consistency: An Introduction
392(3)
5.7 Crosscutting Issues
395(5)
5.8 Putting It All Together: Multicore Processors and Their Performance
400(5)
5.9 Fallacies and Pitfalls
405(4)
5.10 Concluding Remarks
409(3)
5.11 Historical Perspectives and References
412(20)
Case Studies and Exercises
412(20)
Amr Zaky
David A. Wood
Chapter 6 Warehouse-Scale Computers to Exploit Request-Level and Data-Level Parallelism
6.1 Introduction
432(4)
6.2 Programming Models and Workloads for Warehouse-Scale Computers
436(5)
6.3 Computer Architecture of Warehouse-Scale Computers
441(5)
6.4 Physical Infrastructure and Costs of Warehouse-Scale Computers
446(9)
6.5 Cloud Computing: The Return of Utility Computing
455(6)
6.6 Crosscutting Issues
461(3)
6.7 Putting It All Together: A Google Warehouse-Scale Computer
464(7)
6.8 Fallacies and Pitfalls
471(4)
6.9 Concluding Remarks
475(1)
6.10 Historical Perspectives and References
476
Case Studies and Exercises
476
Parthasarathy Ranganathan
Appendix A Instruction Set Principles
A.1 Introduction
2(1)
A.2 Classifying Instruction Set Architectures
3(4)
A.3 Memory Addressing
7(6)
A.4 Type and Size of Operands
13(1)
A.5 Operations in the Instruction Set
14(2)
A.6 Instructions for Control Flow
16(5)
A.7 Encoding an Instruction Set
21(3)
A.8 Crosscutting Issues: The Role of Compilers
24(8)
A.9 Putting It All Together: The MIPS Architecture
32(7)
A.10 Fallacies and Pitfalls
39(6)
A.11 Concluding Remarks
45(2)
A.12 Historical Perspective and References
47
Exercises
47
Gregory D. Peterson
Appendix B Review of Memory Hierarchy
B.1 Introduction
2(14)
B.2 Cache Performance
16(6)
B.3 Six Basic Cache Optimizations
22(18)
B.4 Virtual Memory
40(9)
B.5 Protection and Examples of Virtual Memory
49(8)
B.6 Fallacies and Pitfalls
57(2)
B.7 Concluding Remarks
59(1)
B.8 Historical Perspective and References
59
Exercises
60
Amr Zaky
Appendix C Pipelining: Basic and Intermediate Concepts
C.1 Introduction
2(9)
C.2 The Major Hurdle of Pipelining---Pipeline Hazards
11(19)
C.3 How Is Pipelining Implemented?
30(13)
C.4 What Makes Pipelining Hard to Implement?
43(8)
C.5 Extending the MIPS Pipeline to Handle Multicycle Operations
51(10)
C.6 Putting It All Together: The MIPS R4000 Pipeline
61(9)
C.7 Crosscutting Issues
70(10)
C.8 Fallacies and Pitfalls
80(1)
C.9 Concluding Remarks
81(1)
C.10 Historical Perspective and References
81
Updated Exercises
82
Diana Franklin
Online Appendices
Appendix D Storage Systems
Appendix E Embedded Systems
Thomas M. Conte
Appendix F Interconnection Networks
Timothy M. Pinkston
Jose Duato
Appendix G Vector Processors in More Depth
Krste Asanovic
Appendix H Hardware and Software for VLIW and EPIC
Appendix I Large-Scale Multiprocessors and Scientific Applications
Appendix J Computer Arithmetic
David Goldberg
Appendix K Survey of Instruction Set Architectures
Appendix L Historical Perspectives and References
References 1(1)
Index 1
ACM named John L. Hennessy a recipient of the 2017 ACM A.M. Turing Award for pioneering a systematic, quantitative approach to the design and evaluation of computer architectures with enduring impact on the microprocessor industry. John L. Hennessy is a Professor of Electrical Engineering and Computer Science at Stanford University, where he has been a member of the faculty since 1977 and was, from 2000 to 2016, its tenth President. Prof. Hennessy is a Fellow of the IEEE and ACM; a member of the National Academy of Engineering, the National Academy of Science, and the American Philosophical Society; and a Fellow of the American Academy of Arts and Sciences. Among his many awards are the 2001 Eckert-Mauchly Award for his contributions to RISC technology, the 2001 Seymour Cray Computer Engineering Award, and the 2000 John von Neumann Award, which he shared with David Patterson. He has also received seven honorary doctorates. David Patterson is the Pardee Professor of Computer Science, Emeritus at the University of California at Berkeley, which he joined after graduating from UCLA in 1977.His teaching has been honored by the Distinguished Teaching Award from the University of California, the Karlstrom Award from ACM, and the Mulligan Education Medal and Undergraduate Teaching Award from IEEE. Prof. Patterson received the IEEE Technical Achievement Award and the ACM Eckert-Mauchly Award for contributions to RISC, and he shared the IEEE Johnson Information Storage Award for contributions to RAID. He also shared the IEEE John von Neumann Medal and the C & C Prize with John Hennessy. Like his co-author, Prof. Patterson is a Fellow of the American Academy of Arts and Sciences, the Computer History Museum, ACM, and IEEE, and he was elected to the National Academy of Engineering, the National Academy of Sciences, and the Silicon Valley Engineering Hall of Fame. He served on the Information Technology Advisory Committee to the U.S. President, as chair of the CS division in the Berkeley EECS department, as chair of the Computing Research Association, and as President of ACM. This record led to Distinguished Service Awards from ACM, CRA, and SIGARCH.
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