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E-raamat: Computer Arithmetic and Verilog HDL Fundamentals

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(Santa Clara University, California, USA)
  • Formaat: 971 pages
  • Ilmumisaeg: 19-Dec-2017
  • Kirjastus: CRC Press Inc
  • ISBN-13: 9781439811276
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Computer Arithmetic and Verilog HDL FundamentalsSuurem pilt
  • Formaat: 971 pages
  • Ilmumisaeg: 19-Dec-2017
  • Kirjastus: CRC Press Inc
  • ISBN-13: 9781439811276
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Verilog Hardware Description Language (HDL) is the state-of-the-art method for designing digital and computer systems. Ideally suited to describe both combinational and clocked sequential arithmetic circuits, Verilog facilitates a clear relationship between the language syntax and the physical hardware. It provides a very easy-to-learn and practical means to model a digital system at many levels of abstraction.

Computer Arithmetic and Verilog HDL Fundamentals details the steps needed to master computer arithmetic for fixed-point, decimal, and floating-point number representations for all primary operations. Silvaco Internationals SILOS, the Verilog simulator used in these pages, is simple to understand, yet powerful enough for any application. It encourages users to quickly prototype and de-bug any logic function and enables single-stepping through the Verilog source code. It also presents drag-and-drop abilities.

Introducing the three main modeling methodsdataflow, behavioral, and structuralthis self-contained tutorial











Covers the number systems of different radices, such as octal, decimal, hexadecimal, and binary-coded variations





Reviews logic design fundamentals, including Boolean algebra and minimization techniques for switching functions





Presents basic methods for fixed-point addition, subtraction, multiplication, and division, including the use of decimals in all four operations





Addresses floating-point addition and subtraction with several numerical examples and flowcharts that graphically illustrate steps required for true addition and subtraction for floating-point operands





Demonstrates floating-point division, including the generation of a zero-biased exponent

Designed for electrical and computer engineers and computer scientists, this book leaves nothing unfinished, carrying design examples through to completion. The goal is practical proficiency. To this end, each chapter includes problems of varying complexity to be designed by the reader.

Arvustused

"Cavanagh has provided readers with a very large work on the topics of addition, subtraction, multiplication, and division. The student who completes a course based on this work will have achieved a great deal. Summing Up: Recommended." CHOICE, June 2010

Preface xv
Chapter 1 Number Systems and Number Representations 1
1.1 Number Systems
1
1.1.1 Binary Number System
4
1.1.2 Octal Number System
6
1.1.3 Decimal Number System
8
1.2 Number Representations
12
1.2.1 Sign Magnitude
13
1.2.2 Diminished-Radix Complement
15
1.2.3 Radix Complement
18
1.3 Problems
22
Chapter 2 Logic Design Fundamentals 25
2.1 Boolean Algebra
25
2.2 Minimization Techniques
32
2.2.1 Algebraic Minimization
32
2.2.2 Karnaugh Maps
33
2.2.3 Quine-McCluskey Algorithm
39
2.3 Combinational Logic
44
2.3.1 Multiplexers
47
2.3.2 Decoders
53
2.3.3 Encoders
56
2.3.4 Comparators
58
2.4 Sequential Logic
60
2.4.1 Counters
62
2.4.2 Moore Machines
71
2.4.3 Mealy Machines
78
2.5 Problems
84
Chapter 3 Introduction to Verilog HDL 93
3.1 Built-In Primitives
94
3.2 User-Defined Primitives
108
3.3 Dataflow Modeling
118
3.3.1 Continuous Assignment
118
3.4 Behavioral Modeling
129
3.4.1 Initial Statement
129
3.4.2 Always Statement
129
3.4.3 Interstatement Delay
133
3.4.4 Interstatement Delay
133
3.4.5 Blocking Assignments
133
3.4.6 Nonblocking Assignments
136
3.4.7 Conditional Statements
138
3.4.8 Case Statement
141
3.4.9 Loop Statements
150
3.5 Structural Modeling
154
3.5.1 Module Instantiation
154
3.5.2 Design Examples
155
3.6 Problems
179
Chapter 4 Fixed-Point Addition 183
4.1 Ripple-Carry Addition
184
4.2 Carry Lookahead Addition
191
4.3 Carry-Save Addition
201
4.3.1 Multiple-Bit Addition
201
4.3.2 Multiple-Operand Addition
206
4.4 Memory-Based Addition
212
4.5 Carry-Select Addition
216
4.6 Serial Addition
227
4.7 Problems
234
Chapter 5 Fixed-Point Subtraction 237
5.1 Twos Complement Subtraction
238
5.2 Ripple-Carry Subtraction
243
5.3 Carry Lookahead Addition/Subtraction
250
5.4 Behavioral Addition/Subtraction
267
5.5 Problems
271
Chapter 6 Fixed-Point Multiplication 275
6.1 Sequential Add-Shift Multiplication
276
6.1.1 Sequential Add-Shift Multiplication Hardware Algorithm
278
6.1.2 Sequential Add-Shift Multiplication — Version 1
282
6.1.3 Sequential Add-Shift Multiplication — Version 2
285
6.2 Booth Algorithm Multiplication
289
6.3 Bit-Pair Recoding Multiplication
304
6.4 Array Multiplication
318
6.5 Table Lookup Multiplication
329
6.6 Memory-Based Multiplication
339
6.7 Multiple-Operand Multiplication
344
6.8 Problems
353
Chapter 7 Fixed-Point Division 359
7.1 Sequential Shift-Add/Subtract Restoring Division
360
7.1.1 Restoring Division — Version 1
362
7.1.2 Restoring Division — Version 2
368
7.2 Sequential Shift-Add/Subtract Nonrestoring Division
374
7.3 SRT Division
382
7.3.1 SRT Division Using Table Lookup
393
7.3.2 SRT Division Using the Case Statement
397
7.4 Multiplicative Division
402
7.5 Array Division
408
7.6 Problems
423
Chapter 8 Decimal Addition 427
8.1 Addition with Sum Correction
427
8.2 Addition Using Multiplexers
437
8.3 Addition with Memory-Based Correction
444
8.4 Addition with Biased Augend
454
8.5 Problems
460
Chapter 9 Decimal Subtraction 463
9.1 Subtraction Examples
464
9.2 Two-Decade Addition/Subtraction Unit for A+B and A–B
467
9.3 Two-Decade Addition/Subtraction Unit for A+B, A–B, and B–A
481
9.4 Problems
491
Chapter 10 Decimal Multiplication 493
10.1 Binary-to-BCD Conversion
493
10.2 Multiplication Using Behavioral Modeling
495
10.3 Multiplication Using Structural Modeling
498
10.4 Multiplication Using Memory
510
10.5 Multiplication Using Table Lookup
524
10.6 Problems
528
Chapter 11 Decimal Division 529
11.1 Restoring Division — Version 1
529
11.2 Restoring Division — Version 2
538
11.3 Division Using Table Lookup
545
11.4 Problems
550
Chapter 12 Floating-Point Addition 551
12.1 Floating-Point Format
552
12.2 Biased Exponents
554
12.3 Floating-Point Addition
557
12.4 Overflow and Underflow
560
12.5 General Floating-Point Organization
561
12.6 Verilog HDL Implementation
564
12.7 Problems
569
Chapter 13 Floating-Point Subtraction 571
13.1 Numerical Examples
573
13.2 Flowcharts
581
13.3 Verilog HDL Implementations
584
13.3.1 True Addition
584
13.3.2 True Subtraction — Version 1
589
13.3.3 True Subtraction — Version 2
593
13.3.4 True Subtraction — Version 3
598
13.3.5 True Subtraction — Version 4
603
13.4 Problems
608
Chapter 14 Floating-Point Multiplication 611
14.1 Double Bias
613
14.2 Flowcharts
614
14.3 Numerical Examples
616
14.4 Verilog HDL Implementations
618
14.4.1 Floating-Point Multiplication — Version 1
618
14.4.2 Floating-Point Multiplication — Version 2
624
14.5 Problems
631
Chapter 15 Floating-Point Division 633
15.1 Zero Bias
635
15.2 Exponent Overflow/Underflow
638
15.3 Flowcharts
641
15.4 Numerical Examples
643
15.5 Problems
646
Chapter 16 Additional Floating-Point Topics 649
16.1 Rounding Methods
649
16.1.1 Truncation Rounding
650
16.1.2 Adder-Based Rounding
651
16.1.3 Von Neumann Rounding
653
16.2 Guard Bits
654
16.3 Verilog HDL Implementations
654
16.3.1 Adder-Based Rounding Using Memory
655
16.3.2 Adder-Based Rounding Using Combinational Logic
660
16.3.3 Adder-Based Rounding Using Behavioral Modeling
668
16.3.4 Combined Truncation, Adder-Based, and von Neumann Rounding
674
16.4 Problems
680
Chapter 17 Additional Topics in Computer Arithmetic 685
17.1 Residue Checking
686
17.1.1 Dataflow Modeling
690
17.1.2 Structural Modeling
693
17.2 Parity-Checked Shift Register
717
17.3 Parity Prediction
723
17.4 Condition Codes for Addition
738
17.5 Logical and Algebraic Shifters
747
17.5.1 Behavioral Modeling
748
17.5.2 Structural Modeling
753
17.6 Arithmetic and Logic Units
760
17.6.1 Four-Function Arithmetic and Logic Unit
760
17.6.2 Sixteen-Function Arithmetic and Logic Unit
764
17.7 Count-Down Counter
771
17.8 Shift Registers
775
17.8.1 Parallel-In, Serial-Out Shift Register
775
17.8.2 Serial-In, Serial-Out Shift Register
778
17.8.3 Parallel-In, Serial-In, Serial-Out Shift Register
782
17.8.4 Serial-In, Parallel-Out Shift Register
787
17.9 Problems
795
Appendix A Verilog HDL Designs for Select Logic Functions 801
A.1 AND Gate
801
A.2 NAND Gate
806
A.3 OR Gate
809
A.4 NOR Gate
811
A.5 Exclusive-OR Function
814
A.6 Exclusive-NOR Function
818
A.7 Multiplexers
822
A.8 Decoders
825
A.9 Encoders
829
A.10 Priority Encoder
833
A.11 Binary-to-Gray Code Converter
836
A.12 Adder/Subtractor
843
Appendix B Event Queue 849
B.1 Event Handling for Dataflow Assignments
849
B.2 Event Handling for Blocking Assignments
854
B.3 Event Handling for Nonblocking Assignments
857
B.4 Event Handling for Mixed Blocking and Nonblocking Assignments
861
Appendix C Verilog HDL Project Procedure 865
Appendix D Answers to Select Problems 867
Chapter 1 Number Systems and Number Representations
867
Chapter 2 Logic Design Fundamentals
869
Chapter 3 Introduction to Verilog HDL
873
Chapter 4 Fixed-Point Addition
883
Chapter 5 Fixed-Point Subtraction
887
Chapter 6 Fixed-Point Multiplication
891
Chapter 7 Fixed-Point Division
897
Chapter 8 Decimal Addition
903
Chapter 9 Decimal Subtraction
907
Chapter 10 Decimal Multiplication
908
Chapter 11 Decimal Division
912
Chapter 12 Floating-Point Addition
913
Chapter 13 Floating-Point Subtraction
915
Chapter 14 Floating-Point Multiplication
918
Chapter 15 Floating-Point Division
924
Chapter 16 Additional Floating-Point Topics
926
Chapter 17 Additional Topics in Computer Arithmetic
932
Index 943
Joseph Cavanagh is an adjunct professor in the computer engineering department at Santa Clara University in California.
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