Preface |
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xi | |
Author |
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xxi | |
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Chapter 1 Introduction and Historic Perspective |
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1 | (46) |
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Introduction And Historic Perspective |
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1 | (44) |
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6 | (2) |
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Attributes of the First Computers |
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8 | (1) |
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9 | (2) |
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11 | (2) |
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13 | (1) |
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Classification of Computers |
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13 | (2) |
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15 | (3) |
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18 | (2) |
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20 | (3) |
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1970s Computers: The First Mainframes |
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23 | (2) |
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1980s Computers: The Last Mainframes |
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25 | (1) |
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"The Network Is the Computer" |
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26 | (2) |
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28 | (1) |
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29 | (3) |
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32 | (1) |
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33 | (1) |
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34 | (1) |
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35 | (7) |
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42 | (1) |
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43 | (2) |
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45 | (2) |
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Chapter 2 Data Representation |
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47 | (38) |
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47 | (23) |
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48 | (1) |
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49 | (1) |
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50 | (1) |
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50 | (4) |
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Representing Real Numbers |
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54 | (1) |
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Converting Natural Numbers |
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54 | (3) |
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57 | (1) |
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57 | (1) |
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Negative Numbers Representation |
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58 | (3) |
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61 | (2) |
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63 | (2) |
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Additions and Subtractions |
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65 | (2) |
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67 | (1) |
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68 | (2) |
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70 | (15) |
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Range of Floating-Point Numbers |
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72 | (2) |
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74 | (1) |
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75 | (3) |
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Adding Floating-Point Numbers |
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78 | (1) |
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Multiplying Floating-Point Numbers |
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79 | (2) |
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Decimal Numbers Representations |
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81 | (1) |
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82 | (3) |
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Chapter 3 Hardware Architecture |
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85 | (12) |
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85 | (10) |
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86 | (2) |
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88 | (2) |
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90 | (3) |
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93 | (2) |
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95 | (1) |
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95 | (2) |
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Chapter 4 Central Processing Unit |
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97 | (88) |
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Part I Central Processing Unit |
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97 | (25) |
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97 | (2) |
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99 | (4) |
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Accumulator-Based Architecture |
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103 | (2) |
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Memory--Register Architecture |
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105 | (4) |
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Register--Register Architecture |
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109 | (3) |
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112 | (1) |
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113 | (2) |
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115 | (1) |
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116 | (2) |
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Processor's Internal Clock |
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118 | (1) |
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"Iron Law" of Processor Performance |
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119 | (3) |
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Cycles Per Instruction-Based Metric |
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122 | (12) |
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125 | (2) |
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127 | (4) |
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Calculating and Presenting the Results Obtained |
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131 | (1) |
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132 | (2) |
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Part II Central Processing Unit |
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134 | (51) |
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134 | (4) |
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138 | (3) |
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141 | (4) |
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145 | (3) |
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148 | (2) |
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Instruction-Level Parallelism |
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150 | (4) |
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Instruction-Level Parallelism Problems |
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154 | (2) |
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Instruction-Level Parallelism Hazards |
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156 | (1) |
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157 | (1) |
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Resources' Access Conflicts Hazards |
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158 | (4) |
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162 | (3) |
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165 | (12) |
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177 | (1) |
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177 | (5) |
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182 | (1) |
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183 | (2) |
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185 | (52) |
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185 | (52) |
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187 | (1) |
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188 | (3) |
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191 | (3) |
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194 | (5) |
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Estimating the Processor's Utilization |
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199 | (3) |
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202 | (3) |
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205 | (10) |
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215 | (5) |
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220 | (5) |
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225 | (1) |
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226 | (5) |
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231 | (1) |
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232 | (2) |
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234 | (3) |
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237 | (20) |
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237 | (20) |
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243 | (4) |
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247 | (3) |
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250 | (3) |
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Multiple Processor Architectures |
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253 | (2) |
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255 | (2) |
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257 | (38) |
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257 | (38) |
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261 | (3) |
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264 | (7) |
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271 | (2) |
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273 | (4) |
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Extending the Bus Concept |
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277 | (3) |
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Bus Expansion beyond the System Boundaries |
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280 | (1) |
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281 | (7) |
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288 | (5) |
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293 | (2) |
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Chapter 8 Input and Output |
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295 | (16) |
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295 | (16) |
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Methods for Performing I/O |
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296 | (8) |
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Operating System Considerations |
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304 | (1) |
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305 | (4) |
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309 | (1) |
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309 | (2) |
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311 | (30) |
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311 | (30) |
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311 | (1) |
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312 | (4) |
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316 | (2) |
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318 | (1) |
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319 | (1) |
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320 | (2) |
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322 | (3) |
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325 | (2) |
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Redundant Array of Inexpensive Disks |
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327 | (9) |
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Storage Attached Network (SAN) |
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336 | (2) |
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Network Attached Storage (NAS) |
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338 | (1) |
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338 | (3) |
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Chapter 10 Additional Architectures |
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341 | (26) |
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341 | (26) |
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341 | (9) |
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350 | (1) |
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Service-Oriented Architecture |
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351 | (3) |
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354 | (1) |
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355 | (5) |
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360 | (4) |
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364 | (3) |
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Chapter 11 Software Architectures |
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367 | (46) |
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367 | (45) |
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367 | (1) |
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368 | (1) |
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Client/Server Architecture |
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369 | (2) |
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Peer-to-Peer (P2P) Architecture |
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371 | (4) |
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375 | (2) |
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377 | (3) |
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Object-Oriented Architecture |
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380 | (5) |
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Service-Oriented Architecture |
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385 | (3) |
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CORBA: Common Object Request Broker Architecture |
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388 | (3) |
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Component Object Model (COM) and Distributed COM (DCOM) |
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391 | (2) |
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393 | (6) |
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Java 2 Enterprise Edition |
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399 | (3) |
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Aspect-Oriented Architecture |
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402 | (3) |
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405 | (5) |
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410 | (2) |
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412 | (1) |
Bibliography |
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413 | (8) |
Glossary |
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421 | (16) |
Index |
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437 | |