The book provides accurate FDTD models for on-chip interconnects, covering most recent advancements in materials and design. Furthermore, depending on the geometry and physical configurations, different electrical equivalent models for CNT and GNR based interconnects are presented. Based on the electrical equivalent models the performance comparison among the Cu, CNT and GNR-based interconnects are also discussed in the book. The proposed models are validated with the HSPICE simulations.
The book introduces the current research scenario in the modeling of on-chip interconnects. It presents the structure, properties, and characteristics of graphene based on-chip interconnects and the FDTD modeling of Cu based on-chip interconnects. The model considers the non-linear effects of CMOS driver as well as the transmission line effects of interconnect line that includes coupling capacitance and mutual inductance effects. In a more realistic manner, the proposed model includes the effect of width-dependent MFP of the MLGNR while taking into account the edge roughness.
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1 Introduction to On-Chip Interconnects and Modeling |
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1 | (10) |
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1 | (1) |
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1.2 Evolution of Interconnect Materials |
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2 | (2) |
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1.2.1 Carbon Nanotubes (CNTs) |
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3 | (1) |
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1.2.2 Graphene Nanoribbons (GNRs) |
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4 | (1) |
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1.3 Modeling of On-Chip Interconnects |
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4 | (2) |
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1.4 Introduction to FDTD Method |
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6 | (5) |
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1.4.1 Central Difference Approximation |
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7 | (1) |
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8 | (3) |
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2 Interconnect Modeling, CNT and GNR Structures, Properties, and Characteristics |
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11 | (32) |
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2.1 Interconnect Modeling Approaches |
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11 | (3) |
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2.1.1 Lumped Model with CMOS Driver |
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11 | (1) |
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2.1.2 Distributed Model with Resistive Driver |
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12 | (1) |
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2.1.3 Distributed Model with CMOS Driver |
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13 | (1) |
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14 | (15) |
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2.2.1 Basic Structure of CNTs |
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14 | (4) |
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2.2.2 Semiconducting and Metallic CNTs |
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18 | (2) |
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2.2.3 Properties and Characteristics of CNTs |
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20 | (2) |
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2.2.4 Conductivity Comparison |
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22 | (2) |
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2.2.5 MWCNT Interconnect Modeling |
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24 | (4) |
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2.2.6 MWCNT Performance Analysis |
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28 | (1) |
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29 | (14) |
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2.3.1 Basic Structure of GNRs |
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29 | (2) |
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2.3.2 Semiconducting and Metallic GNRs |
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31 | (1) |
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2.3.3 Properties and Characteristics of GNRs |
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31 | (2) |
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2.3.4 Conductivity Comparison |
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33 | (1) |
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2.3.5 MLGNR Interconnect Modeling |
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34 | (2) |
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2.3.6 MLGNR Performance Analysis |
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36 | (2) |
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38 | (5) |
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3 FDTD Model for Crosstalk Analysis of CMOS Gate-Driven Coupled Copper Interconnects |
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43 | (18) |
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43 | (1) |
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44 | (3) |
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3.3 FDTD Model of CMOS Gate-Driven Cu Interconnects |
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47 | (6) |
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3.3.1 FDTD Model of Coupled Interconnects |
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48 | (2) |
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3.3.2 Incorporation of Boundary Constraints |
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50 | (3) |
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3.4 Validation of the Model |
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53 | (3) |
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3.5 Extended Three Coupled Interconnect Lines |
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56 | (2) |
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58 | (3) |
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59 | (2) |
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4 FDTD Model for Crosstalk Analysis of Multiwall Carbon Nanotube (MWCNT) Interconnects |
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61 | (20) |
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61 | (2) |
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4.2 Equivalent Single Conductor Model of the MWCNT Interconnect |
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63 | (5) |
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65 | (1) |
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65 | (2) |
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67 | (1) |
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4.3 FDTD Model of MWCNT Interconnect |
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68 | (4) |
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4.3.1 The MWCNT Interconnect Line |
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68 | (2) |
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4.3.2 Boundary Condition at Near-End Terminal |
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70 | (1) |
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4.3.3 Boundary Condition at Far-End Terminal |
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71 | (1) |
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4.4 Validation of the Model |
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72 | (3) |
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75 | (2) |
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4.5.1 Sensitivity Analysis for Number of Conducting Channels |
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75 | (1) |
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4.5.2 Sensitivity Analysis for Contact Resistance |
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76 | (1) |
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77 | (4) |
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77 | (4) |
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5 Crosstalk Modeling with Width Dependent MFP in MLGNR Interconnects Using FDTD Technique |
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81 | (16) |
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81 | (1) |
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5.2 Equivalent Single Conductor Model of the MLGNR Interconnect |
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82 | (4) |
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5.2.1 Transient Analysis of MTL and ESC Models |
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85 | (1) |
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5.3 FDTD Model of the MLGNR Interconnect |
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86 | (3) |
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5.4 Results and Discussion |
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89 | (6) |
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5.4.1 Analysis of Mean Free Path, Resistance, and Propagation Delay with Rough Edges |
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90 | (1) |
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5.4.2 Crosstalk-Induced Delay |
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91 | (2) |
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5.4.3 Performance Comparison Between Cu and MLGNR Interconnects |
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93 | (2) |
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95 | (2) |
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95 | (2) |
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6 An Efficient US-FDTD Model for Crosstalk Analysis of On-Chip Interconnects |
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97 | (18) |
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97 | (1) |
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6.2 Development of Proposed US-FDTD Model |
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98 | (9) |
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6.2.1 Modeling of Coupled On-Chip Interconnects |
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99 | (2) |
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6.2.2 Modeling of CMOS Driver |
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101 | (1) |
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6.2.3 Modeling of Driver-Interconnect-Load |
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102 | (4) |
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106 | (1) |
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6.3 Simulation Setup and Results |
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107 | (6) |
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108 | (1) |
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6.3.2 Crosstalk Induced Noise Peak, Width and Delay Analysis |
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109 | (1) |
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6.3.3 Unconditional Stability of the Proposed Model |
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110 | (1) |
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6.3.4 Efficiency of the Proposed Model |
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111 | (1) |
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6.3.5 Comparison with 3D Simulations |
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112 | (1) |
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6.4 Performance Comparison of Cu, MWCNT and MLGNR Interconnects |
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113 | (2) |
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115 | (1) |
| References |
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115 | |
Brajesh Kumar Kaushik received the B.E. degree in Electronics and Communication Engineering from the D.C.R. University of Science and Technology (formerly C. R. State College of Engineering), Murthal, Haryana, in 1994, the M.Tech degree in Engineering Systems from Dayalbagh Educational Institute, Agra, India, in 1997, and the PhD degree under AICTE-QIP scheme from the Indian Institute of Technology Roorkee, Roorkee, India, in 2007. He served at Vinytics Peripherals Pvt. Ltd., Delhi from 1997 to 1998 as the Research and Development Engineer for microprocessor-, microcontroller-, and DSP processor-based systems.
He joined the department of Electronics and Communication Engineering, G.B. Pant Engineering College, Pauri Garhwal, Uttarakhand, India as a Lecturer in July, 1998, where later he served as an Assistant Professor from May 2005 to May 2006 and an Associate Professor from May 2006 to December 2009. He is currently serving as Associate Professor in the departmentof Electronics and Communication Engineering, Indian Institute of Technology Roorkee. His research interests include high-speed interconnects, low-power VLSI design, carbon nanotube-based designs, organic thin-film transistor design and modeling, and spintronics-based devices and circuits. He has published extensively in several national and international journals and conferences of repute. Dr. Kaushik is a reviewer of many international journals belonging to various publication houses such as IEEE, IET, Elsevier, Springer, Emerald, Taylor and Francis, etc. He has also delivered many keynote addresses in reputed international and national conferences. He holds the position of Editor and Editor-in-Chief of various journals in the field of VLSI and Microelectronics. Dr. Kaushik is Editor-in-Chief of International Journal of VLSI Design and Communication System (VLSICS), AIRCC Publishing Corporation. He also holds the position of Editor of Microelectronics Journal (MEJ), Elsevier Inc.; Journal of Engineering, Design and Technology (JEDT), Emerald Group Publishing Limited; and Journal of Electrical and Electronics Engineering Research (JEEER), Academic Journals. He is a Senior Member of IEEE and has received many awards and recognitions from the International Biographical Center, Cambridge, U.K. His name has been listed in Marquis Whos Who in Science and Engineering and Marquis Whos Who in the World. Vobulapuram Ramesh Kumar received the B.Tech degree in Electronics and Communication Engineering from Bapatla Engineering College, Andhra Pradesh, in 2007, and the M.Tech degree from National Institute of Technology Hamirpur, in 2010. He is currently working towards the PhD degree from Indian Institute of Technology Roorkee, India. His current research interests include time domain numerical methods to approach fast transients characterization techniques, modeling of VLSI on-chip interconnects, carbon based nano interconnects and through silicon vias.
Amalendu Patnaik received his PhD in Electronics from Berhampur University in 2003. He is currently serving as Associate Professor in the department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee. He served as a Lecturer in National Institute of Science and Technology, Berhampur, India. During 2004-05, he has been to University of New Mexico, Albuquerque, USA as a Visiting Scientist. He has published more than 50 papers in journal and conferences, co-authored one book on Engineering Electromagnetics, and one book chapter on Neural Network for Antennas in Modern Antenna Handbook from Wiley. Besides this, he has presented his research work as short courses/tutorials in many national and international conferences. His current research interests include array signal processing, application of soft-computing techniques in Electromagnetics, CAD for patch antennas, EMI and EMC. He wasawarded the IETE Sir J. C. Bose Award in 1998 and BOYSCAST Fellowship in 2004-05 from Department of Science and Technology, Government of India. Dr. Patnaik is a life member of Indian Society for Technical Education (ISTE), Senior Member of IEEE and IEEE AP-S Region 10 Distinguished Speaker.
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