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Differential and Higher Order Attacks |
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A First-Order DPA Attack Against AES in Counter Mode with Unknown Initial Counter |
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1 | (10) |
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Gaussian Mixture Models for Higher-Order Side Channel Analysis |
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11 | (17) |
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Side Channel Cryptanalysis of a Higher Order Masking Scheme |
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28 | (17) |
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Random Number Generation and Device Identification |
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High-Speed True Random Number Generation with Logic Gates Only |
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45 | (18) |
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FPGA Intrinsic PUFs and Their Use for IP Protection |
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63 | (18) |
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Logic Styles: Masking and Routing |
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Evaluation of the Masked Logic Style MDPL on a Prototype Chip |
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81 | (14) |
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Masking and Dual-Rail Logic Don't Add Up |
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95 | (12) |
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DPA-Resistance Without Routing Constraints? |
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107 | (14) |
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Efficient Algorithms for Embedded Processors |
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On the Power of Bitslice Implementation on Intel Core2 Processor |
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121 | (14) |
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Highly Regular Right-to-Left Algorithms for Scalar Multiplication |
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135 | (13) |
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MAME: A Compression Function with Reduced Hardware Requirements |
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148 | (18) |
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Collision Attacks and Fault Analysis |
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Collision Attacks on AES-Based MAC: Alpha-MAC |
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166 | (15) |
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Secret External Encodings Do Not Prevent Transient Fault Analysis |
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181 | (14) |
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Two New Techniques of Side-Channel Cryptanalysis |
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195 | (14) |
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High Speed AES Implementations |
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AES Encryption Implementation and Analysis on Commodity Graphics Processing Units |
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209 | (18) |
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Multi-gigabit GCM-AES Architecture Optimized for FPGAs |
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227 | (12) |
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Arithmetic Operators for Pairing-Based Cryptography |
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239 | (17) |
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FPGA Design of Self-certified Signature Verification on Koblitz Curves |
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256 | (16) |
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How to Maximize the Potential of FPGA Resources for Modular Exponentiation |
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272 | (17) |
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Implementation Cost of Countermeasures |
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TEC-Tree: A Low-Cost, Parallelizable Tree for Efficient Defense Against Memory Replay Attacks |
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289 | (16) |
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Power Analysis Resistant AES Implementation with Instruction Set Extensions |
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305 | (15) |
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Security Issues for RF and RFID |
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Power and EM Attacks on Passive 13.56 MHz RFID Devices |
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320 | (14) |
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RFID Noisy Reader How to Prevent from Eavesdropping on the Communication? |
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334 | (12) |
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RF-DNA: Radio-Frequency Certificates of Authenticity |
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346 | (18) |
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Special Purpose Hardware for Cryptanalysis |
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CAIRN 2: An FPGA Implementation of the Sieving Step in the Number Field Sieve Method |
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364 | (14) |
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Collision Search for Elliptic Curve Discrete Logarithm over GF (2m) with FPGA |
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378 | (16) |
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Guerric Meurice de Dormale |
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A Hardware-Assisted Realtime Attack on A5/2 Without Precomputations |
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394 | (19) |
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Differential Behavioral Analysis |
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413 | (14) |
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Information Theoretic Evaluation of Side-Channel Resistant Logic Styles |
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427 | (16) |
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Francois-Xavier Standaert |
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Problems and Solutions for Lightweight Devices |
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On the Implementation of a Fast Prime Generation Algorithm |
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443 | (7) |
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Present: An Ultra-Lightweight Block Cipher |
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450 | (17) |
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Author Index |
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467 | |