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E-raamat: Design for High Performance, Low Power, and Reliable 3D Integrated Circuits

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  • Kirjastus: Springer-Verlag New York Inc.
  • Keel: eng
  • ISBN-13: 9781441995421
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Design for High Performance, Low Power, and Reliable 3D Integrated CircuitsSuurem pilt
  • Formaat: PDF+DRM
  • Ilmumisaeg: 27-Nov-2012
  • Kirjastus: Springer-Verlag New York Inc.
  • Keel: eng
  • ISBN-13: 9781441995421
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This book describes a variety of algorithms and software tools, dedicated to the physical design of through-silicon-via (TSV) based, three-dimensional integrated circuits. It provides full details of all key algorithms, for maximum understanding and utility.

This book provides readers with a variety of algorithms and software tools, dedicated to the physical design of through-silicon-via (TSV) based, three-dimensional integrated circuits. It describes numerous “manufacturing-ready” GDSII-level layouts of TSV-based 3D ICs developed with the tools covered in the book. This book will also feature sign-off level analysis of timing, power, signal integrity, and thermal analysis for 3D IC designs. Full details of the related algorithms will be provided so that the readers will be able not only to grasp the core mechanics of the physical design tools, but also to be able to reproduce and improve upon the results themselves. This book will also offer various design-for-manufacturability (DFM), design-for-reliability (DFR), and design-for-testability (DFT) techniques that are considered critical to the physical design process.
Part I High Performance and Low Power 3D IC Designs
1 Regular Versus Irregular TSV Placement for 3D IC
3(38)
1.1 Introduction
3(2)
1.2 Existing Works
5(1)
1.3 Preliminaries
6(5)
1.3.1 Design of 3D ICs
6(2)
1.3.2 Maximum Allowable TSV Count
8(1)
1.3.3 Minimum TSV Count
9(2)
1.3.4 Tradeoff Between Wirelength and TSV Count
11(1)
1.4 3D IC Physical Design Flow
11(4)
1.4.1 Partitioning
12(2)
1.4.2 TSV Insertion and Placement
14(1)
1.4.3 Routing
15(1)
1.5 3D Global Placement Algorithm
15(5)
1.5.1 Overview of Force-Directed Placement
16(1)
1.5.2 Overview of Our 3D Placement Algorithm
17(1)
1.5.3 Cell Placement in 3D ICs
17(1)
1.5.4 Pre-placement of TSVs in TSV Site Scheme
18(1)
1.5.5 Wirelength Computation for 3D Nets
19(1)
1.6 TSV Assignment Algorithm
20(4)
1.6.1 Optimum Solution for TSV Assignment
20(2)
1.6.2 MST-Based TSV Assignment
22(2)
1.6.3 Placement-Based TSV Assignment
24(1)
1.7 Experimental Results
24(14)
1.7.1 Wirelength and Runtime Comparison
25(3)
1.7.2 Metal Layers and Silicon Area Comparison
28(1)
1.7.3 Wirelength and TSV Count Tradeoff
28(1)
1.7.4 Wirelength, Die Area, and Die Count Tradeoff
29(1)
1.7.5 TSV Co-placement Versus TSV Site
30(5)
1.7.6 Impact of TSV Size
35(1)
1.7.7 Timing and Power Comparison
35(3)
1.8 Conclusions
38(3)
References
38(3)
2 Steiner Routing for 3D IC
41(34)
2.1 Introduction
41(2)
2.2 Existing Works
43(2)
2.3 Preliminaries
45(2)
2.3.1 Problem Formulation
45(1)
2.3.2 Overview of the Approach
46(1)
2.4 3D Steiner Tree Construction
47(6)
2.4.1 Overview of the Algorithm
47(2)
2.4.2 Computing Connection Point and TSV Location
49(3)
2.4.3 Optimization of Delay Equations
52(1)
2.5 3D Tree Refinement with TSV Relocation
53(7)
2.5.1 Overview of the Algorithm
53(1)
2.5.2 Movable Range
53(1)
2.5.3 Compact Thermal Analysis
54(1)
2.5.4 Non-linear Programming Formulation
55(3)
2.5.5 Integer Linear Programming Formulation
58(1)
2.5.6 Fast Integer Linear Programming Formulation
59(1)
2.6 Experimental Results
60(9)
2.6.1 Experimental Setting
60(1)
2.6.2 Tree Construction Results
61(2)
2.6.3 Delay and Wirelength Distribution
63(1)
2.6.4 TSV Relocation Results
64(2)
2.6.5 Impact of TSV Dimension and Parasitics
66(2)
2.6.6 Impact of Bonding Style
68(1)
2.6.7 Two-die versus four-die Stacking
68(1)
2.7 Conclusions
69(6)
Appendix
69(3)
References
72(3)
3 Buffer Insertion for 3D IC
75(24)
3.1 Introduction
75(1)
3.2 Problem Definition
76(1)
3.3 Motivational Example
77(1)
3.4 Delay and Slew Models
78(3)
3.4.1 Target 3D IC and TSV Structure
78(1)
3.4.2 Delay and Slew Models for Gates
79(2)
3.4.3 Delay and Slew Models for Nets
81(1)
3.5 Ginneken-3D Algorithm
81(1)
3.6 Bottom-Up Slew Propagation DP
82(7)
3.6.1 Generation of Sink Solutions
83(1)
3.6.2 Slew Binning and Slew-Based Pruning
83(3)
3.6.3 Merging Solutions
86(2)
3.6.4 Buffer Insertion
88(1)
3.6.5 Multiple Solution Tracking
89(1)
3.7 3D IC Design Methodologies
89(1)
3.8 Experimental Results
90(7)
3.8.1 Buffer Insertion Results
91(1)
3.8.2 Endpoint Slack Histograms
92(2)
3.8.3 Impact of TSV Capacitance
94(1)
3.8.4 Critical Path Analysis
94(3)
3.9 Conclusions
97(2)
References
97(2)
4 Low Power Clock Routing for 3D IC
99(30)
4.1 Introduction
99(2)
4.2 Existing Works
101(1)
4.3 Preliminaries
102(2)
4.3.1 Electrical and Physical Model of 3D Clock Network
102(1)
4.3.2 Problem Formulation
103(1)
4.4 3D Clock Tree Synthesis
104(5)
4.4.1 Overview
104(1)
4.4.2 3D Abstract Tree Generation
104(4)
4.4.3 Slew-Aware Buffering and Embedding
108(1)
4.5 Extension of 3D-MMM Algorithm
109(4)
4.6 Experimental Results
113(14)
4.6.1 Simulation Settings
113(2)
4.6.2 Impact of TSV Count and Parasitic Capacitance
115(1)
4.6.3 Exhaustive Search Results
116(1)
4.6.4 3D-MMM-ext Algorithm Results
117(6)
4.6.5 Low-Slew 3D Clock Routing
123(2)
4.6.6 Scaling the Supply Voltage
125(1)
4.6.7 Comparison with Existing Work
126(1)
4.7 Conclusions
127(2)
References
127(2)
5 Power Delivery Network Design for 3D IC
129(24)
5.1 Introduction
129(2)
5.2 Existing Works
131(1)
5.3 P/G TSV Impact on 3D IC Layouts
131(3)
5.4 Non-regular Power/Ground TSV Placement Algorithm
134(5)
5.4.1 Equivalent Circuit for Series Resistors
134(2)
5.4.2 Equivalent Circuit Modeling for P/G TSV Placement
136(1)
5.4.3 Non-regular P/G TSV Placement Algorithm
137(2)
5.4.4 Validation Methodology
139(1)
5.5 Power/Ground TSV Placement Results
139(5)
5.5.1 IR-Drop Analysis Results for 2D and 3D Designs
140(1)
5.5.2 Impact of 3D P/G Network Topology on IR-Drop
141(2)
5.5.3 Non-regular P/G TSV Placement Algorithm
143(1)
5.6 TSV RC Variation
144(3)
5.6.1 TSV Resistance Variation
144(1)
5.6.2 TSV Capacitance Variation
144(1)
5.6.3 Validation Methodology
145(2)
5.7 Variation Analysis Results
147(3)
5.7.1 Impact of TSV RC Variation Range
147(1)
5.7.2 Impact of Number of Variation Sources
148(1)
5.7.3 Impact of Number of C4 Bumps
148(1)
5.7.4 Impact of TSV Size
149(1)
5.8 Conclusions
150(3)
References
150(3)
6 3D Clock Routing for Pre-bond Testability
153(36)
6.1 Introduction
153(1)
6.2 Existing Works
154(1)
6.3 Preliminaries
155(2)
6.3.1 3D Abstract Tree Generation
155(2)
6.3.2 3D-MMM Algorithm and Pre-bond Testing
157(1)
6.4 Problem Formulation and Terminology
157(1)
6.5 Pre-bond Testable Clock Routing
158(6)
6.5.1 Overview
158(1)
6.5.2 TSV-Buffer Insertion
159(2)
6.5.3 Redundant Tree Insertion
161(1)
6.5.4 Putting It Together
162(1)
6.5.5 Multiple-Die Extension
163(1)
6.6 Buffering for Wirelength and Slew Control
164(2)
6.6.1 Wirelength Balancing with Clock Buffers
164(1)
6.6.2 Slew Rate Control with Clock Buffers
165(1)
6.7 Experimental Results
166(17)
6.7.1 TSV-Buffer and TG Model Validation
167(1)
6.7.2 Sample Trees and Waveforms
168(1)
6.7.3 Wirelength, Skew, and Power Results
169(3)
6.7.4 Comparison with the Single-TSV Approach
172(1)
6.7.5 Impact of TSV Bound on Power
172(3)
6.7.6 Impact of TSV-Buffer Insertion
175(1)
6.7.7 Impact of Clock Source Location
175(2)
6.7.8 Impact of Buffer Load Constraint on Power and Slew
177(2)
6.7.9 Impact of TSV Capacitance
179(2)
6.7.10 Impact of TSV Bound and Capacitance
181(2)
6.7.11 Comparison with Existing Work
183(1)
6.8 Conclusions
183(6)
References
184(5)
Part II Electrical Reliability in 3D IC Designs
7 TSV-to-TSV Coupling Analysis and Optimization
189(16)
7.1 Introduction
189(1)
7.2 Existing Studies
190(1)
7.3 TSV-Induced Coupling Model
190(3)
7.3.1 Coupling Sources Due to TSVs
190(1)
7.3.2 TSV-to-TSV Coupling Modeling
191(2)
7.4 Full-Chip Signal Integrity Analysis
193(3)
7.4.1 Full Chip 3D SI Analysis Flow
193(1)
7.4.2 Design and Analysis Results
194(2)
7.5 TSV-to-TSV Coupling Reduction
196(7)
7.5.1 Why TSV Spacing Is Inefficient
196(1)
7.5.2 TSV Shielding to Alleviate Coupling
197(3)
7.5.3 Buffer Insertion to Alleviate Coupling
200(2)
7.5.4 Overall Comparison
202(1)
7.6 Conclusions
203(2)
References
203(2)
8 TSV Current Crowding and Power Integrity
205(26)
8.1 Introduction
205(2)
8.2 Existing Works
207(1)
8.3 Current Crowding in 3D IC
207(4)
8.3.1 Current Density Distribution Inside a TSV
207(2)
8.3.2 Power-Wire-to-TSV Interface
209(1)
8.3.3 TSV-Diameter-to-Wire-Thickness Ratio
209(2)
8.3.4 Impact of Current Crowding on IR Drop
211(1)
8.4 TSV Current Crowding Model
211(6)
8.4.1 3D Resistance Network for TSV Modeling
212(2)
8.4.2 Modeling of the Transition Region
214(1)
8.4.3 Modeling Accuracy
214(1)
8.4.4 Impact of XY-Mesh Size
215(1)
8.4.5 Chip-Scale PDN Circuit Model
216(1)
8.5 Experimental Results
217(11)
8.5.1 Chip-Scale Noise Analysis
217(3)
8.5.2 Impact of TSV Mesh Size
220(1)
8.5.3 Impact of TSV and C4 Offset
220(2)
8.5.4 Impact of Power Wire Density
222(2)
8.5.5 Impact of TSV and C4 Count
224(1)
8.5.6 Impact of TSV Diameter
224(1)
8.5.7 Power Integrity in Large-Scale 3D PDN
224(4)
8.6 Conclusions
228(3)
References
228(3)
9 Modeling of Atomic Concentration at the Wire-to-TSV Interface
231(22)
9.1 Introduction
231(1)
9.2 Existing Works
232(2)
9.3 Preliminaries
234(1)
9.3.1 Mean Time to Failure
234(1)
9.3.2 Grains and Grain Boundaries
234(1)
9.4 Modeling Approach and Settings
235(5)
9.4.1 Electro-Migration Equations
236(1)
9.4.2 Atomic Flux and Atomic Flux Divergence
237(1)
9.4.3 Effect of Activation Energy and Atomic Concentration
237(1)
9.4.4 Effect of Current
238(1)
9.4.5 Effect of Thermal and Stress
238(1)
9.4.6 Model Settings
239(1)
9.5 Experimental Results
240(8)
9.5.1 Impact of Current Crowding
240(4)
9.5.2 Impact of Current Direction and Density
244(1)
9.5.3 Impact of Temperature
245(2)
9.5.4 Impact of Grain Size
247(1)
9.5.5 Impact of Activation Energy
248(1)
9.6 Conclusions
248(5)
References
249(4)
Part III Thermal Reliability in 3D IC Designs
10 Multi-objective Architectural Floorplanning for 3D IC
253(32)
10.1 Introduction
253(2)
10.2 Existing Works
255(1)
10.3 Simulation Infrastructure
256(5)
10.3.1 Micro-architectural Model
256(1)
10.3.2 Dynamic Power Modeling
257(1)
10.3.3 Leakage Power Modeling
258(1)
10.3.4 Thermal Modeling
258(1)
10.3.5 Integrated Design Flow
259(2)
10.4 2D Micro-architectural Floorplanning
261(5)
10.4.1 LP-Based 2D Floorplanning
261(4)
10.4.2 Stochastic Refinement
265(1)
10.5 Extension to 3D Floorplanning
266(5)
10.5.1 3D Extension of Architectural Simulation
266(1)
10.5.2 Vertical Overlap Optimization
267(1)
10.5.3 Bonding-Aware Layer Partitioning
268(1)
10.5.4 LP-Based 3D Floorplanning
269(1)
10.5.5 3D Stochastic Refinement
270(1)
10.6 Experimental Results
271(9)
10.6.1 Experimental Setting
271(1)
10.6.2 Comparison to Existing 3D Floorplanner
271(1)
10.6.3 Floorplanning Results
272(3)
10.6.4 Optimization Method Comparison
275(1)
10.6.5 Architectural Analysis
276(3)
10.6.6 Fidelity Study
279(1)
10.7 Conclusions
280(5)
References
281(4)
11 Thermal-Aware Gate-Level Placement for 3D IC
285(24)
11.1 Introduction
285(1)
11.2 Existing Works
286(1)
11.3 Motivation
286(1)
11.4 Evaluation Flow
287(4)
11.4.1 Power Analysis for 3D ICs
288(1)
11.4.2 GDSII-Level Thermal Analysis
289(2)
11.5 Global 3D Placement Algorithms
291(3)
11.5.1 Design Flow
292(1)
11.5.2 Force-Directed 3D Placement
292(1)
11.5.3 TSV Spread and Alignment
293(1)
11.6 Thermal Coupling-Aware Placement
294(6)
11.6.1 For Cell Movement
295(3)
11.6.2 For TSV Movement
298(1)
11.6.3 Balancing the Forces
299(1)
11.7 Experimental Results
300(7)
11.7.1 Impact of TSV Density Uniformity
300(1)
11.7.2 Comparison with State-of-the-Art
301(3)
11.7.3 Power and Thermal Maps
304(1)
11.7.4 Temperature versus Wirelength Tradeoff
304(2)
11.7.5 Runtime Results
306(1)
11.8 Conclusions
307(2)
References
307(2)
12 3D IC Cooling with Micro-Fluidic Channels
309(36)
12.1 Introduction
309(2)
12.2 Existing Works
311(1)
12.3 Routing Resource Modeling
311(5)
12.3.1 Signal Interconnects
312(1)
12.3.2 Power Interconnects
313(2)
12.3.3 Thermal Interconnects
315(1)
12.4 Design and Analysis Flow
316(5)
12.4.1 Overview of 3D Physical Design
316(1)
12.4.2 Power Noise Analysis
317(1)
12.4.3 Thermal Analysis for T-TSV Case
318(1)
12.4.4 Thermal Analysis for MFC Case
319(2)
12.5 Design of Experiments
321(3)
12.5.1 Classical DOE
321(1)
12.5.2 Advanced DOE
321(1)
12.5.3 Finding Best Response Models
322(1)
12.5.4 Optimization with Response Surface Models
323(1)
12.6 Experimental Results
324(15)
12.6.1 Experimental Settings
324(1)
12.6.2 Comparison of 2D and 3D IC Designs
325(1)
12.6.3 Comparison of T-TSV and MFC Based Cooling
326(1)
12.6.4 Varying One Input Factor at a Time
327(2)
12.6.5 Classical DOE
329(2)
12.6.6 Advanced DOE: T-TSV Case
331(3)
12.6.7 Advanced DOE: MFC Case
334(3)
12.6.8 Comparison to Gradient Search
337(2)
12.6.9 Discussions
339(1)
12.7 Conclusions
339(6)
References
340(5)
Part IV Mechanical Reliability in 3D IC Designs
13 Mechanical Reliability Analysis and Optimization for 3D ICs
345(34)
13.1 Introduction
345(1)
13.2 Detailed Baseline Modeling
346(9)
13.2.1 3D FEA Simulation
348(1)
13.2.2 Impact of TSV Liner and Landing Pad
348(2)
13.2.3 Impact of Cu Diffusion Barrier
350(2)
13.2.4 Stress Influence Zone
352(1)
13.2.5 Anisotropic Material Property of Silicon
353(2)
13.3 Full-Chip Reliability Analysis
355(10)
13.3.1 Linear Superposition Principle
356(1)
13.3.2 Stress Analysis with Multiple TSVs
356(1)
13.3.3 Mechanical Reliability Analysis
357(1)
13.3.4 Validation of Linear Superposition Method
357(1)
13.3.5 Handling Anisotropic Silicon
358(2)
13.3.6 Limitation of Linear Superposition Method
360(2)
13.3.7 Full-Chip Analysis Flow
362(2)
13.3.8 Scalability of Algorithm
364(1)
13.4 Experimental Results
365(12)
13.4.1 Overall Comparison
366(1)
13.4.2 Impact of TSV Pitch
367(2)
13.4.3 Impact of Relative TSV Orientation
369(1)
13.4.4 Impact of TSV Size
369(2)
13.4.5 Impact of Landing Pad Size
371(1)
13.4.6 Impact of Liner Thickness
371(2)
13.4.7 Impact of Chip Operation Temperature
373(1)
13.4.8 Reliability of Block-Level 3D Design
374(1)
13.4.9 Impact of TSV Re-placement
375(1)
13.4.10 Comparison Between Isotropic and Anisotropic Si
376(1)
13.5 Conclusion
377(2)
References
377(2)
14 Impact of Mechanical Stress on Timing Variation for 3D IC
379(36)
14.1 Introduction
379(2)
14.2 Existing Works
381(1)
14.3 Preliminaries
382(2)
14.3.1 TSV/STI-Induced Mechanical Stress
382(1)
14.3.2 Stress Impact on Mobility Variations
383(1)
14.4 Design Methodologies
384(1)
14.5 Mobility Variation Under TSV-Induced Stress
385(6)
14.5.1 Mobility Variation Under Single TSV
385(2)
14.5.2 Mobility Variation Under Multiple TSVs
387(4)
14.6 Mobility Variation Under STI-Induced Stress
391(4)
14.7 Mobility Variation Under both TSV and STI-Induced Stress
395(3)
14.8 Full-Chip 3D Timing Analysis Under Mechanical Stress
398(4)
14.8.1 Timing Analysis for 3D ICs
398(1)
14.8.2 Timing Library Construction Under Mobility Variation
399(3)
14.9 Experimental Results
402(10)
14.9.1 Full Chip Mobility Variation Map
402(1)
14.9.2 Full Chip Timing Analysis Results
403(4)
14.9.3 Placement Optimization Results
407(2)
14.9.4 Impact of TSV Diameter on Timing
409(3)
14.10 Conclusions
412(3)
References
413(2)
15 Chip/Package Co-analysis of Mechanical Stress for 3D IC
415(28)
15.1 Introduction
415(1)
15.2 Motivation
416(3)
15.3 3D IC/Package Stress Modeling
419(8)
15.3.1 Stress Tensor and Von Mises Criterion
419(1)
15.3.2 3D IC/Package Simulation Structure
420(1)
15.3.3 Impact of Die Stacking
421(1)
15.3.4 Impact of Thickness of Substrate
422(1)
15.3.5 Impact of Multiple Die Stacking
423(1)
15.3.6 Isotropic Versus Anisotropic Si Property
424(2)
15.3.7 Impact of TSV and Bump Alignment
426(1)
15.4 Handling Full-Chip/Package Co-analysis
427(6)
15.4.1 Lateral and Vertical Linear Superposition
427(2)
15.4.2 Full-Chip/Package Stress Analysis Flow
429(1)
15.4.3 Validation of LVLS
430(1)
15.4.4 Full-Chip/Package Analysis Algorithm
431(2)
15.5 Experimental Results
433(7)
15.5.1 Impact of Package-Bump and Micro-Bump
434(1)
15.5.2 Impact of Bump Size
435(1)
15.5.3 Impact of TSV Size
436(1)
15.5.4 Impact of Pitch
437(1)
15.5.5 Case Study I: Wide-I/O DRAM
438(1)
15.5.6 Case Study II: Block-Level 3D IC
439(1)
15.6 Conclusions
440(3)
References
441(2)
16 3D Chip/Package Co-analysis of Stress-Induced Timing Variations
443(24)
16.1 Introduction
443(1)
16.2 Existing Works
444(1)
16.3 Stress and Mobility Variation Model
444(5)
16.3.1 Need for True 3D Chip/Package Stress Model
444(2)
16.3.2 Piezo-Resistivity
446(1)
16.3.3 Mobility Variation: 2D Versus 3D Stress
447(2)
16.4 Chip/Package Stress Impact on Mobility Variation
449(4)
16.4.1 Linear Superposition Principle
449(2)
16.4.2 Mobility Variations from Chip/Package Elements
451(2)
16.5 Chip/Package Stress-Aware Timing Analysis
453(1)
16.6 Experimental Results
453(11)
16.6.1 2D Versus 3D Stress Impact on Mobility and Timing
454(3)
16.6.2 Impact of KOZ Size
457(3)
16.6.3 Case Study: Block-Level 3D Designs
460(2)
16.6.4 Case Study: Wide-I/O Style 3D Designs
462(2)
16.6.5 Key Findings and Design Guides
464(1)
16.7 Conclusions
464(3)
References
464(3)
17 TSV Interfacial Crack Analysis and Optimization
467(26)
17.1 Introduction
467(1)
17.2 Preliminaries
468(2)
17.2.1 TSV Interfacial Crack
468(1)
17.2.2 Energy Release Rate
468(2)
17.3 TSV Interfacial Crack Modeling
470(6)
17.3.1 3D FEA Simulation
470(1)
17.3.2 Impact of TSV Liner and Landing Pad
471(2)
17.3.3 Impact of Pitch and Angle among TSVs
473(2)
17.3.4 Relative Importance of Pitch Over Angle
475(1)
17.4 DOE-Based Full-Chip TSV Interfacial Crack Modeling
476(7)
17.4.1 Designing Experiments
477(1)
17.4.2 ERR Model for Regular TSV Placement
478(2)
17.4.3 ERR Model for Irregular TSV Placement
480(1)
17.4.4 Quality of ERR Model
481(1)
17.4.5 Full-Chip Analysis Flow
482(1)
17.5 Experimental Results
483(5)
17.5.1 Impact of KOZ
483(2)
17.5.2 Impact of Liner
485(1)
17.5.3 Reliability of Block-Level 3D Design
486(1)
17.5.4 Summary and Key Findings
487(1)
17.6 Conclusions
488(5)
References
489(4)
Part V Other Topics
18 Ultra High Density Logic Designs Using Monolithic 3D Integration
493(22)
18.1 Introduction
493(2)
18.2 Existing Works
495(1)
18.3 Design Methodologies
495(5)
18.3.1 Library Construction
495(2)
18.3.2 Standard Cell Design
497(2)
18.3.3 Full-Chip Physical Layout
499(1)
18.4 Routing Congestion Issues in Monolithic 3D ICs
500(2)
18.5 Impact of Additional Metal Layers
502(4)
18.5.1 Metal Layer Stack Options
502(1)
18.5.2 RC Modeling of Via Stack in 4BM Case
503(1)
18.5.3 Delay and Power Calculations in MI-T Designs
504(2)
18.5.4 Simulation Results and Discussions
506(1)
18.6 Impact of Reduced Metal Width and Spacing
506(6)
18.7 Impact of Device and Interconnect Scaling
512(1)
18.8 Conclusions
513(2)
References
514(1)
19 Impact of TSV Scaling on 3D IC Design Quality
515(22)
19.1 Introduction
515(2)
19.2 Preliminaries
517(1)
19.2.1 Design Overhead of TSVs
517(1)
19.2.2 Motivation
517(1)
19.3 Library Development Flow
518(3)
19.3.1 Overall Development Flow
518(1)
19.3.2 Interconnect Layers
518(2)
19.3.3 Standard Cell Library
520(1)
19.4 Comparison of 45, 22, and 16 nm Libraries
521(3)
19.4.1 Gate Delay and Input Capacitance
522(1)
19.4.2 Interconnect Layers
523(1)
19.4.3 Full-Chip 2D Design
524(1)
19.5 Full-Chip 3D IC Design and Analysis Methodology
524(1)
19.6 Experimental Results
525(9)
19.6.1 Simulation Settings
525(1)
19.6.2 Impact on Silicon Area
526(1)
19.6.3 Impact on Wirelength
527(3)
19.6.4 Impact on Performance
530(1)
19.6.5 Impact on Power
531(1)
19.6.6 Impact of the Number of Dies
532(2)
19.7 Conclusions
534(3)
References
534(3)
20 3D-MAPS: 3D Massively Parallel Processor with Stacked Memory
537
20.1 Introduction
537(2)
20.2 Architecture Design
539(2)
20.2.1 Instruction Set Architecture
539(1)
20.2.2 Single-Core Architecture
540(1)
20.2.3 Multi-core Architecture
540(1)
20.2.4 Off-Chip Interface
541(1)
20.3 Benchmark Applications
541(2)
20.4 TSV and Stacking Technology
543(1)
20.5 Physical Design of 3D-MAPS
544(4)
20.5.1 Overview of 3D-MAPS Layout
544(1)
20.5.2 Single Core and Memory Tile Design
545(1)
20.5.3 Top-Level Design and Power Delivery Network
546(2)
20.6 Design Evaluation and Verification of 3D-MAPS
548(6)
20.6.1 Timing and Signal Integrity Analysis
548(3)
20.6.2 Power and Power Supply Noise Analysis
551(2)
20.6.3 DRC and LVS
553(1)
20.7 Package and Board Design
554(2)
20.8 Die Shots and Measurement Results
556(2)
20.9 Conclusions
558
References
559
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