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E-raamat: Design And Modeling For 3d Ics And Interposers

(Ulsan Nat'l Inst Of Sci' & Tech (Unist), Korea), (Georgia Inst Of Technology, Usa)
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3D Integration is being touted as the next semiconductor revolution. This book provides a comprehensive coverage on the design and modeling aspects of 3D integration, in particularly, focus on its electrical behavior. Looking from the perspective the Silicon Via (TSV) and Glass Via (TGV) technology, the book introduces 3DICs and Interposers as a technology, and presents its application in numerical modeling, signal integrity, power integrity and thermal integrity. The authors underscored the potential of this technology in design exchange formats and power distribution.
Preface vii
Acknowledgement xix
Chapter 1 System Integration and Modeling Concepts
1(60)
1.1 Moore's Law
1(2)
1.2 IC Integration Vs System Integration -- What is the Difference?
3(2)
1.3 History of Integration -- An Overview
5(11)
1.3.1 3D Integration -- Is it the Next Semiconductor Revolution?
10(4)
1.3.2 What Comes Next?
14(2)
1.4 Primary Drivers for 3D Integration
16(6)
1.4.1 Thirst for More Bandwidth at Low Power
16(3)
1.4.2 Large Chips Sink Ships
19(1)
1.4.3 Heterogeneous Integration to Continue More Than Moore Scaling
20(2)
1.5 Role of the Interposer in 3D Integration
22(9)
1.5.1 Three Embodiments of the Interposer
24(2)
1.5.2 Silicon or Glass or X for Interposer
26(5)
1.6 Modeling and Simulation
31(25)
1.6.1 Electrical Modeling and 3D Path Finder
36(2)
1.6.1.1 Full Wave Electromagnetic Analysis
38(3)
1.6.1.2 Physics Based Analytical Models
41(1)
1.6.1.3 3D Path Finder
42(2)
1.6.2 Design Exchange Format
44(1)
1.6.2.1 Example of a Two Die Stack
45(1)
1.6.2.2 IR Drop
46(5)
1.6.2.3 Thermal Management
51(4)
1.6.2.4 Move Towards a DEF by the Engineering Community
55(1)
1.7 Summary
56(5)
References
57(4)
Chapter 2 Modeling of Cylindrical Interconnections
61(54)
2.1 Introduction
61(3)
2.2 Specialized Basis Functions
64(1)
2.3 Electric Field Integral Equation (EFIE) with Cylindrical CMBF for Resistance and Inductance Extraction
64(19)
2.3.1 Cylindrical Conduction Mode Basis Functions (CMBF)
65(2)
2.3.2 EFIE Formulation
67(1)
2.3.2.1 Voltage Equation
68(2)
2.3.2.2 Partial Impedances
70(4)
2.3.2.3 Equivalent Circuit
74(2)
2.3.3 Efficiency Enhancements and Implementation
76(1)
2.3.3.1 Controlling the Number of PE-Mode Basis Functions
77(2)
2.3.3.2 Multi-Function Method (MFM)
79(2)
2.3.4 R-L Extraction Example: Comparison with PEEC Method
81(2)
2.4 Scalar Potential Integral Equation (SPIE) with Cylindrical AMBF for Conductance and Capacitance Extraction
83(8)
2.4.1 Cylindrical Accumulation Mode Basis Functions (AMBF)
83(2)
2.4.2 SPIE Formulation in Free Space
85(2)
2.4.3 SPIE Formulation Considering Homogeneous Media
87(1)
2.4.3.1 Vector and Scalar Potentials
87(2)
2.4.3.2 Equivalent Circuit Model of Conductor
89(2)
2.5 Broadband Equivalent RLC Network
91(4)
2.6 Inclusion of Planar Structures
95(6)
2.6.1 Combining Cylindrical and Planar Structures
96(1)
2.6.1.1 Conventional PEEC Method
97(3)
2.6.2 Infinite Ground Plane: Image Method for Modeling Infinite Ground
100(1)
2.7 Examples with Bonding Wires
101(5)
2.7.1 Three JEDEC4 Type Bonding Wires
102(1)
2.7.2 Bonding Wires in a Plastic Ball Grid Array (PBGA) Package
103(1)
2.7.3 Bonding Wires in Three Stacked ICs: The Effect of Vertical Coupling
104(2)
2.8 Examples with Vias
106(2)
2.8.1 Glass Interposer Vias
106(1)
2.8.2 Via Chains
107(1)
2.9 Example of Package on Package
108(2)
2.10 Summary
110(5)
References
111(4)
Chapter 3 Electrical Modeling of Through Silicon Vias
115(64)
3.1 Benefits of Through Silicon Vias
115(2)
3.2 Challenges in Modeling Through Silicon Vias
117(2)
3.3 Propagating Modes in Through Silicon Vias -- An Electromagnetic Perspective
119(7)
3.4 Physics Based Modeling of Through Silicon Vias
126(5)
3.4.1 Creating an Equivalent Circuit
127(1)
3.4.2 Computing Scattering Parameters
128(3)
3.5 Rigorous Electromagnetic Modeling
131(20)
3.5.1 Defining the Complex Permittivity of Silicon Substrate
133(1)
3.5.2 Modeling the Conductor Currents
133(2)
3.5.3 Modeling the Charge Density
135(3)
3.5.4 Modeling the Polarization Current
138(5)
3.5.5 Combining the Current and Charge Contributions
143(2)
3.5.6 Equivalent Circuit Simplification
145(3)
3.5.7 Extraction of RLGC and S-parameters
148(3)
3.6 Modeling of Conical Through Silicon Via
151(8)
3.6.1 Conical TSV Modeling
152(3)
3.6.2 Simulation Results of Conical TSVs
155(2)
3.6.3 Modeling of Complex TSV Structures
157(2)
3.7 MOS Capacitance Effect
159(9)
3.7.1 Extraction of MOS Capacitance
160(3)
3.7.2 Full Depletion Approximation
163(1)
3.7.3 Numerical Analysis
164(2)
3.7.4 Capacitance Vs. Bias Voltage
166(1)
3.7.5 Impact of Bias Voltage on Insertion Loss and Model Development
166(2)
3.8 Consideration of MOS Capacitance Effect in Electromagnetic Modeling
168(5)
3.9 Time Domain Response
173(2)
3.10 Summary
175(4)
References
176(3)
Chapter 4 Electrical Performance and Signal Integrity
179(66)
4.1 Process Optimization
179(7)
4.1.1 Insertion Loss Variation for a TSV Pair
180(2)
4.1.2 Capacitance Variation of TSV
182(3)
4.1.3 Insertion Loss of a TSV Pair with Substrate Bias
185(1)
4.2 Cross Talk in Interposers
186(14)
4.2.1 Cross Talk Measurements and Correlation to Model
186(2)
4.2.2 Coupling between TSVs
188(5)
4.2.3 Effect of Temperature
193(1)
4.2.3.1 Modeling Temperature Effects
194(1)
4.2.3.2 Effect of Temperature on Cross Talk
195(2)
4.2.4 Revisiting Crosstalk
197(3)
4.3 Via Arrays
200(19)
4.3.1 5x5 TSV Array
201(4)
4.3.2 Suppressing Cross Talk
205(5)
4.3.3 20x20 TSV Array
210(1)
4.3.4 TSV Array and Keep Out Zone
211(3)
4.3.5 High Frequency Electrical -- Thermal Modeling
214(5)
4.4 Interposers
219(16)
4.4.1 Through Glass Vias
220(2)
4.4.2 Response of Power and Ground Planes
222(5)
4.4.3 Signal Integrity
227(4)
4.4.4 A More Rigorous Look at Simultaneous Switching Noise and Signal Integrity
231(4)
4.5 Modeling and Design Challenges
235(7)
4.6 Summary
242(3)
References
242(3)
Chapter 5 Power Distribution, Return Path Discontinuities and Thermal Management
245(50)
5.1 Power Distribution -- An Overview
246(3)
5.2 Power Distribution for 3D Integration
249(11)
5.2.1 Power Distribution Impedance
252(3)
5.2.2 Power Supply Noise
255(5)
5.3 Current Paths in IC and Package
260(4)
5.4 Signal and Power Integrity -- Does One Affect the Other?
264(8)
5.4.1 Impact of PDN Impedance on Signal Insertion Loss
265(3)
5.4.2 Impact of Insertion Loss and PDN Impedance on Jitter and Amplitude of Clock Signal
268(1)
5.4.3 Impact of Insertion Loss and PDN Impedance on Jitter and Noise of PRBS Signal
269(3)
5.5 Challenges for Addressing Power Distribution in 3D ICs and Interposers
272(1)
5.6 Thermal Management and its Effect on Power Distribution
273(18)
5.6.1 What is Joule Heating
274(1)
5.6.2 Modeling Electrical-Thermal Effects in the Steady State
274(3)
5.6.3 Finite Volume Formulation
277(1)
5.6.3.1 Voltage Distribution Equation
278(1)
5.6.3.2 Heat Equation for Solid Medium with Convection Boundary Condition
279(1)
5.6.3.3 Heat Equation for Fluid Flow
280(3)
5.6.3.4 Solving the Coupled Equations
283(1)
5.6.4 Examples
283(1)
5.6.4.1 Joule Heating Effects using Air and Micro-Fluidic Cooling
283(6)
5.6.4.2 Impact of Silicon and Glass Interposer
289(2)
5.7 Summary
291(4)
References
292(3)
Chapter 6 Alternate Methods for Power Distribution
295(48)
6.1 Introducing Power Transmission Lines
296(6)
6.1.1 Understanding Power Transmission Lines
297(5)
6.2 Constant Current Power Transmission Line (CCPTL)
302(10)
6.2.1 Basic Concept
302(2)
6.2.2 CCPTL Test Vehicle
304(8)
6.3 Pseudo Balanced Power Transmission Line (PBPTL)
312(10)
6.3.1 PBPTL Test Vehicle with Off the Shelf Chips
315(4)
6.3.2 Design and Measurements of Custom Chip
319(3)
6.4 Constant Voltage Power Transmission Line (CVPTL)
322(6)
6.4.1 Design Equations
322(2)
6.4.1.1 Example
324(1)
6.4.2 CVPTL Test Vehicle
325(2)
6.4.3 Measurements and Comparison
327(1)
6.5 Power Calculations
328(3)
6.6 Application of Power Transmission Lines to FPGA
331(1)
6.7 Managing Signal and Power Integrity for 3D ICs
331(8)
6.7.1 Energy Calculations
337(2)
6.8 Summary
339(4)
References
340(3)
Appendix
343(6)
A.1 Derivation of the Solution of the Diffusion Equation (2.1)
343(1)
A.2 Derivation of the Effective Areas
344(1)
A.3 Derivation of the Surface Charge Density Distribution (2.21)
344(1)
A.4 Partial Element Formula of Brick-Type Conductors
345(3)
A.5 Indefinite Integral for Axial Variables in Mutual Inductance between a Cylinder and a Plane
348(1)
Index 349
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