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E-raamat: Design Recipes for FPGAs: Using Verilog and VHDL

3.29/5 (8 hinnangut Goodreads-ist)
(University of Bath and Integra Designs Ltd., UK)
  • Formaat: EPUB+DRM
  • Ilmumisaeg: 01-Oct-2015
  • Kirjastus: Newnes (an imprint of Butterworth-Heinemann Ltd )
  • Keel: eng
  • ISBN-13: 9780080971360
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Design Recipes for FPGAs: Using Verilog and VHDLSuurem pilt
  • Formaat: EPUB+DRM
  • Ilmumisaeg: 01-Oct-2015
  • Kirjastus: Newnes (an imprint of Butterworth-Heinemann Ltd )
  • Keel: eng
  • ISBN-13: 9780080971360
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This book provides a rich toolbox of design techniques and templates to solve practical, every-day problems using FPGAs. Using a modular structure, it provides design techniques and templates at all levels, together with functional code, which you can easily match and apply to your application. Written in an informal and easy to grasp style, this invaluable resource goes beyond the principles of FPGAs and hardware description languages to demonstrate how specific designs can be synthesized, simulated and downloaded onto an FPGA. In addition, the book provides advanced techniques to create ‘real world’ designs that fit the device required and which are fast and reliable to implement.

  • Contains examples that are rewritten and tested in Verilog, the language most widely used by FPGA developers within the industry
  • Describes high-level example applications and provides the building blocks for implementation
  • Demonstrates theory, but enables engineers to immediately start practical work
  • Singles out the most important parts of the language that are needed for design recipes
  • Goes beyond the principles of FPGAs and hardware description languages to demonstrate how specific designs can be synthesized, simulated, and downloaded onto an FPGA

Arvustused

"...a great book for someone wanting to learn HDL design as the examples are crystal-clear, and it can be hard to find real-world HDL examples on the net. The chapter on a CPU design alone will teach one a lot about coding for FPGAs." --Embedded.com

"Design Recipes for FPGAs is an excellent volume for engineers who work with FPGAs either regularly or occasionally... the book provides a handy shelf reference with examples for many useful functional blocks, ranging from relatively small illustrative syntactic and structural examples to more complex concepts. Whether you work in VHDL occasionally or every day, you'll find practical help in this book." --Lewin Edwards, Design Engineer and Technical Author

Muu info

A rich toolbox of practical FPGA design techniques and templates that will enable you to solve practical problems using FPGAs - now updated with examples in Verilog
Preface to the Second Edition xv
Preface to the First Edition xvii
Acknowledgments xix
PART 1 OVERVIEW
1(64)
Chapter 1 Introduction
3(4)
1.1 Overview
3(1)
1.2 Verilog vs. VHDL
3(1)
1.3 Why FPGAs?
4(1)
1.4 Summary
5(2)
Chapter 2 An FPGA Primer
7(10)
2.1 Introduction
7(1)
2.2 FPGA Evolution
7(1)
2.3 Programmable Logic Devices
8(1)
2.4 Field Programmable Gate Arrays
8(4)
2.5 FPGA Design Techniques
12(1)
2.6 Design Constraints using FPGAs
12(1)
2.7 Development Kits and Boards
13(2)
2.8 Summary
15(2)
Chapter 3 A VHDL Primer: The Essentials
17(18)
3.1 Introduction
17(1)
3.2 Entity: Model Interface
18(2)
3.2.1 The Entity Definition
18(1)
3.2.2 Ports
19(1)
3.2.3 Generics
19(1)
3.2.4 Constants
20(1)
3.2.5 Entity Examples
20(1)
3.3 Architecture: Model Behavior
20(1)
3.3.1 Basic Definition of An Architecture
20(1)
3.3.2 Architecture Declaration Section
21(1)
3.3.3 Architecture Statement Section
21(1)
3.4 Process: Basic Functional Unit in VHDL
21(1)
3.5 Basic Variable Types and Operators
22(3)
3.5.1 Constants
22(1)
3.5.2 Signals
23(1)
3.5.3 Variables
23(1)
3.5.4 Boolean Operators
23(1)
3.5.5 Arithmetic Operators
24(1)
3.5.6 Comparison Operators
24(1)
3.5.7 Logical Shifting Functions
24(1)
3.5.8 Concatenation
24(1)
3.6 Decisions and Loops
25(2)
3.6.1 If-Then-Else
25(1)
3.6.2 Case
26(1)
3.6.3 For
26(1)
3.6.4 While and Loop
27(1)
3.6.5 Exit
27(1)
3.6.6 Next
27(1)
3.7 Hierarchical Design
27(3)
3.7.1 Functions
27(1)
3.7.2 Packages
28(1)
3.7.3 Components
29(1)
3.7.4 Procedures
30(1)
3.8 Debugging Models
30(1)
3.8.1 Assertions
30(1)
3.9 Basic Data Types
30(2)
3.9.1 Basic Types
30(1)
3.9.2 Data Type: bit
31(1)
3.9.3 Data Type: Boolean
31(1)
3.9.4 Data Type: Integer
31(1)
3.9.5 Integer Subtypes: Natural
31(1)
3.9.6 Integer Subtypes: Positive
31(1)
3.9.7 Data Type: Character
32(1)
3.9.8 Data Type: Real
32(1)
3.9.9 Data Type: Time
32(1)
3.10 Summary
32(3)
Chapter 4 A Verilog Primer: The Essentials
35(8)
4.1 Introduction
35(1)
4.2 Modules
35(1)
4.3 Connections
36(1)
4.4 Wires and Registers
37(1)
4.5 Defining the Module Behavior
38(1)
4.6 Parameters
39(1)
4.7 Variables
40(1)
4.8 Data Types
40(1)
4.9 Decision Making
40(1)
4.10 Loops
41(1)
4.11 Summary
41(2)
Chapter 5 Design Automation of FPGAs
43(14)
5.1 Introduction
43(1)
5.2 Simulation
43(5)
5.2.1 Simulators
43(1)
5.2.2 Test Benches
44(1)
5.2.3 Test Bench Goals
44(1)
5.2.4 Simple Test Bench: Instantiating Components
45(1)
5.2.5 Adding Stimuli
46(2)
5.2.6 Assertions
48(1)
5.3 Libraries
48(2)
5.3.1 Introduction
48(1)
5.3.2 Using Libraries
49(1)
5.3.3 Std_logic Libraries
49(1)
5.4 std_logic Type Definition
50(1)
5.5 Synthesis
51(1)
5.5.1 Design Flow for Synthesis
51(1)
5.5.2 Synthesis Issues
52(1)
5.6 RTL Design Flow
52(1)
5.7 Physical Design Flow
53(1)
5.8 Place and Route
53(1)
5.8.1 Recursive Cut
53(1)
5.8.2 Simulated Annealing
54(1)
5.9 Timing Analysis
54(1)
5.10 Design Pitfalls
54(2)
5.10.1 Initialization
55(1)
5.10.2 Floating Point Numbers and Operations
55(1)
5.11 Summary
56(1)
Chapter 6 Synthesis
57(8)
6.1 Introduction
57(2)
6.1.1 HDL Supported in RTL Synthesis
57(2)
6.2 Numeric Types
59(1)
6.3 Wait Statements
59(1)
6.4 Assertions
59(1)
6.5 Loops
59(1)
6.6 Some Interesting Cases Where Synthesis May Fail
59(1)
6.7 What Is Being Synthesized?
60(4)
6.7.1 Overall Design Structure
60(1)
6.7.2 Controller
60(3)
6.7.3 Data Path
63(1)
6.8 Summary
64(1)
PART 2 INTRODUCTION TO FPGA APPLICATIONS
65(50)
Chapter 7 High Speed Video Application
67(12)
7.1 Introduction
67(1)
7.2 The Camera Link Interface
68(3)
7.2.1 Hardware Interface
68(1)
7.2.2 Data Rates
68(1)
7.2.3 The Bayer Pattern
69(1)
7.2.4 Memory Requirements
70(1)
7.3 Getting Started
71(1)
7.4 Specifying the Interfaces
71(1)
7.5 Defining the Top Level Design
72(1)
7.6 System Block Definitions and Interfaces
73(3)
7.6.1 Overall System Decomposition
73(1)
7.6.2 Mouse and Keyboard Interfaces
74(1)
7.6.3 Memory Interface
74(1)
7.6.4 The Display Interface: VGA
75(1)
7.7 The Camera Link Interface
76(1)
7.8 The PC Interface
76(1)
7.9 Summary
77(2)
Chapter 8 Simple Embedded Processors
79(36)
8.1 Introduction
79(1)
8.2 A Simple Embedded Processor
79(8)
8.2.1 Embedded Processor Architecture
79(2)
8.2.2 Basic Instructions
81(1)
8.2.3 Fetch Execute Cycle
82(1)
8.2.4 Embedded Processor Register Allocation
83(1)
8.2.5 A Basic Instruction Set
84(1)
8.2.6 Structural or Behavioral?
85(1)
8.2.7 Machine Code Instruction Set
86(1)
8.2.8 Structural Elements of the Microprocessor
86(1)
8.3 A Simple Embedded Processor Implemented in VHDL
87(10)
8.3.1 Processor Functions Package
87(1)
8.3.2 The Program Counter
88(1)
8.3.3 The Instruction Register
89(2)
8.3.4 The Arithmetic and Logic Unit
91(1)
8.3.5 The Memory
92(2)
8.3.6 Microcontroller Controller
94(3)
8.3.7 Summary of a Simple Microprocessor Implemented in VHDL
97(1)
8.4 A Simple Embedded Processor Implemented in Verilog
97(15)
8.4.1 The Program Counter
97(3)
8.4.2 The Instruction Register
100(2)
8.4.3 Memory Data Register
102(2)
8.4.4 Memory Address Register
104(3)
8.4.5 The Arithmetic and Logic Unit
107(3)
8.4.6 The Memory
110(1)
8.4.7 Microcontroller Controller
110(2)
8.4.8 Summary of a Simple Verilog Microprocessor
112(1)
8.5 Soft Core Processors on an FPGA
112(1)
8.6 Summary
113(2)
PART 3 DESIGNER'S TOOLBOX
115(114)
Chapter 9 Digital Filters
117(18)
9.1 Introduction
117(1)
9.2 Converting S Domain to Z Domain
118(1)
9.3 Implementing Z Domain Functions in VHDL
119(5)
9.3.1 Introduction
119(1)
9.3.2 Gain Block
120(1)
9.3.3 Sum and Difference
121(1)
9.3.4 Division Model
122(1)
9.3.5 Unit Delay Model
123(1)
9.4 Basic Low Pass Filter Model
124(3)
9.5 Implementing Z Domain Functions in Verilog
127(6)
9.5.1 Gain Block
127(2)
9.5.2 Sum and Difference
129(2)
9.5.3 Unit Delay Model
131(2)
9.6 Finite Impulse Response Filters
133(1)
9.7 Infinite Impulse Response Filters
133(1)
9.8 Summary
134(1)
Chapter 10 Secure Systems
135(32)
10.1 Introduction to Block Ciphers
135(1)
10.2 Feistel Lattice Structures
135(2)
10.3 The Data Encryption Standard (DES)
137(12)
10.3.1 Introduction
137(3)
10.3.2 DES VHDL Implementation
140(5)
10.3.3 DES Verilog Implementation
145(4)
10.3.4 Validation of DES
149(1)
10.4 Advanced Encryption Standard
149(16)
10.4.1 Implementing AES in VHDL
153(12)
10.5 Summary
165(2)
Chapter 11 Memory
167(18)
11.1 Introduction
167(1)
11.2 Modeling Memory in HDLs
168(1)
11.3 Read Only Memory
168(2)
11.4 Random Access Memory
170(7)
11.5 Synchronous RAM
177(5)
11.6 Flash Memory
182(2)
11.7 Summary
184(1)
Chapter 12 PS/2 Mouse Interface
185(6)
12.1 Introduction
185(1)
12.2 PS/2 Mouse Basics
185(1)
12.3 PS/2 Mouse Commands
185(1)
12.4 PS/2 Mouse Data Packets
186(1)
12.5 PS/2 Operation Modes
186(1)
12.6 PS/2 Mouse with Wheel
187(1)
12.7 Basic PS/2 Mouse Handler VHDL
187(1)
12.8 Modified PS/2 Mouse Handler VHDL
188(1)
12.9 Basic PS/2 Mouse Handler in Verilog
189(1)
12.10 Summary
190(1)
Chapter 13 PS/2 Keyboard Interface
191(6)
13.1 Introduction
191(1)
13.2 PS/2 Keyboard Basics
191(1)
13.3 PS/2 Keyboard Commands
192(1)
13.4 PS/2 Keyboard Data Packets
192(1)
13.5 PS/2 Keyboard Operation Modes
192(3)
13.5.1 Basic PS/2 Keyboard Handler in VHDL
192(1)
13.5.2 Modified PS/2 Keyboard Handler in VHDL
193(1)
13.5.3 Basic PS/2 Keyboard Handler in Verilog
194(1)
13.6 Summary
195(2)
Chapter 14 A Simple VGA Interface
197(12)
14.1 Introduction
197(1)
14.2 Basic Pixel Timing
197(1)
14.3 Image Handling
198(1)
14.4 A VGA Interface in VHDL
198(5)
14.4.1 VHDL Top Level Entity for VGA Handling
198(1)
14.4.2 Horizontal Sync
199(1)
14.4.3 Vertical Sync
200(1)
14.4.4 Horizontal and Vertical Blanking Pulses
201(1)
14.4.5 Calculating the Correct Pixel Data
202(1)
14.5 A VGA Interface in Verilog
203(4)
14.5.1 Verilog Top Level Module for VGA Handling
203(1)
14.5.2 Horizontal Sync
204(1)
14.5.3 Vertical Sync
205(1)
14.5.4 Horizontal and Vertical Blanking Pulses
206(1)
14.5.5 Calculating the Correct Pixel Data
207(1)
14.6 Summary
207(2)
Chapter 15 Serial Communications
209(20)
15.1 Introduction
209(1)
15.2 Manchester Encoding and Decoding
209(1)
15.3 Implementing the Manchester Encoding Scheme using VHDL
210(2)
15.4 Implementing the Manchester Encoding Scheme using Verilog
212(2)
15.5 NRZ (Non-Return-to-Zero) Coding and Decoding
214(1)
15.6 NRZI (Non-Return-to-Zero-Inverted) Coding and Decoding
215(3)
15.6.1 NRZI Coding and Decoding in VHDL
215(1)
15.6.2 NRZI Coding and Decoding in Verilog
216(2)
15.7 RS-232
218(7)
15.7.1 Introduction
218(1)
15.7.2 RS-232 Baud Rate Generator
218(3)
15.7.3 RS-232 Receiver
221(4)
15.8 Universal Serial Bus
225(3)
15.9 Summary
228(1)
PART 4 OPTIMIZING DESIGNS
229(54)
Chapter 16 Design Optimization
231(6)
16.1 Introduction
231(1)
16.2 Techniques for Logic Optimization
231(2)
16.3 Improving Performance
233(1)
16.4 Critical Path Analysis
234(1)
16.5 Summary
235(2)
Chapter 17 Behavioral Modeling in using HDLs
237(6)
17.1 Introduction
237(1)
17.2 How to Go from RTL to Behavioral HDL Descriptions
237(1)
17.3 Implementing the Behavioral Model using VHDL
237(3)
17.4 Implementing the Behavioral Model using Verilog
240(2)
17.5 Summary
242(1)
Chapter 18 Mixed Signal Modeling
243(22)
18.1 Introduction
243(1)
18.2 Basic Modeling Approach for VHDL-AMS
243(1)
18.3 Introduction to VHDL-AMS
244(1)
18.4 VHDL-AMS Analog Pins: TERMINALS
245(1)
18.5 Mixed Domain Modeling
246(1)
18.6 VHDL-AMS Analog Variables: Quantities
246(1)
18.7 Simultaneous Equations in VHDL-AMS
247(1)
18.8 A VHDL-AMS Example: A DC Voltage Source
247(1)
18.9 A VHDL-AMS Example: Resistor
248(1)
18.10 Differential Equations in VHDL-AMS
249(2)
18.11 Mixed-Signal Modeling with VHDL-AMS
251(2)
18.12 A Basic Switch Model
253(2)
18.13 Basic VHDL-AMS Comparator Model
255(1)
18.14 Multiple Domain Modeling
256(1)
18.15 Introduction to Verilog-AMS
257(1)
18.16 Verilog-AMS: Analog ports
258(1)
18.17 Mixed Domain Modeling in Verilog-AMS
258(1)
18.18 Verilog-AMS Analog Variables
259(1)
18.19 Verilog-AMS Analog Equations
259(1)
18.20 A Verilog-AMS Example
260(1)
18.20.1 DC Voltage Source
260(1)
18.20.2 Resistor
260(1)
18.21 Differential Equations in Verilog-AMS
261(1)
18.22 Mixed Signal Modeling with Verilog-AMS
262(1)
18.23 Multiple Domain Modeling using Verilog-AMS
263(1)
18.24 Summary
264(1)
Chapter 19 Design Optimization Example: DES
265(18)
19.1 Introduction
265(1)
19.2 The Data Encryption Standard
265(1)
19.3 MOODS
266(1)
19.4 Initial Design
266(6)
19.4.1 Introduction
266(1)
19.4.2 Overall Structure
266(3)
19.4.3 Data Transformations
269(2)
19.4.4 Key Transformations
271(1)
19.5 Initial Synthesis
272(1)
19.6 Optimizing the Datapath
273(2)
19.6.1 Optimizing the Key Transformations
274(1)
19.7 Final Optimization
275(1)
19.8 Results
276(1)
19.9 Triple DES
276(4)
19.9.1 Introduction
276(1)
19.9.2 Minimum Area Iterative
277(2)
19.9.3 Minimum Latency Pipelined
279(1)
19.10 Comparing the Approaches
280(1)
19.11 Summary
281(2)
References
281(2)
PART 5 FUNDAMENTAL TECHNIQUES
283(78)
Chapter 20 Latches, Flip-Flops, and Registers
285(10)
20.1 Introduction
285(1)
20.2 Latches
285(2)
20.3 Flip-Flops
287(4)
20.4 Registers
291(3)
20.5 Summary
294(1)
Chapter 21 ALU Functions
295(10)
21.1 Introduction
295(1)
21.2 Logic Functions in VHDL
295(4)
21.2.1 1-bit Adder
297(2)
21.3 Structural n-Bit Addition
299(1)
21.4 Logic Functions in Verilog
300(1)
21.5 Configurable n-Bit Addition
301(1)
21.6 Two's Complement
302(2)
21.7 Summary
304(1)
Chapter 22 Finite State Machines in VHDL and Verilog
305(6)
22.1 Introduction
305(1)
22.2 State Transition Diagrams
305(1)
22.3 Implementing Finite State Machines in VHDL
305(3)
22.4 Implementing Finite State Machines in Verilog
308(1)
22.5 Testing the Finite State Machine Model
309(1)
22.6 Summary
309(2)
Chapter 23 Fixed Point Arithmetic
311(10)
23.1 Introduction
311(2)
23.2 Basic Fixed Point Types in VHDL
313(1)
23.3 Fixed Point Functions in VHDL
314(3)
23.3.1 Fixed Point to STD_LOGIC_VECTOR Functions
314(1)
23.3.2 Fixed Point to Real Conversion
315(2)
23.4 Testing the VHDL Fixed Point Functions
317(1)
23.5 Fixed Point Types in Verilog
318(1)
23.6 Floating Point Types in Verilog
319(1)
23.7 Summary
319(2)
Chapter 24 Counters
321(16)
24.1 Introduction
321(1)
24.2 Basic Binary Counter using VHDL
321(3)
24.3 Simple Binary Counter using Verilog
324(1)
24.4 Synthesized Simple Binary Counter
325(2)
24.5 Shift Register
327(4)
24.6 The Johnson Counter
331(2)
24.7 BCD Counter
333(2)
24.8 Summary
335(2)
Chapter 25 Decoders and Multiplexers
337(8)
25.1 Decoders
337(3)
25.2 Multiplexers
340(3)
25.3 Summary
343(2)
Chapter 26 Multiplication
345(10)
26.1 Introduction
345(1)
26.2 Basic Binary Multiplication
345(1)
26.3 VHDL Unsigned Multiplier
346(2)
26.4 Synthesis of the Multiplication Function
348(1)
26.5 Simple Multiplication using VHDL
349(2)
26.6 Simple Multiplication using Verilog
351(2)
26.7 Summary
353(2)
Chapter 27 Simple 7-Segment (LCD) Displays
355(6)
27.1 Introduction
355(1)
27.2 VHDL LCD Module Decoder
355(3)
27.3 Verilog LCD Module Decoder
358(2)
27.4 Summary
360(1)
Bibliography 361(4)
Index 365
Peter Wilson is Professor of Electronic Systems Engineering in the Electronic and Electrical Engineering Department at the University of Bath. After obtaining degrees at Heriot-Watt University in Edinburgh he worked as a Senior Design Engineer with Ferranti, Scotland and then as a Technical Specialist for Analogy, Inc. in Oregon, USA. After obtaining his PhD at the University of Southampton, he joined the faculty and was a member of the Academic staff at the University of Southampton from 2002 till 2015 when he moved to the University of Bath. He has published more than 100 papers and 3 books. Peter Wilson is also a Fellow of the IET, Fellow of the British Computer Society, a Chartered Engineer in the UK and a Senior Member of the IEEE.
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