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E-raamat: Designer's Guide to the Cortex-M Processor Family

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(Technical Specialist, Hitex (UK) Ltd., Coventry, England, UK)
  • Formaat: PDF+DRM
  • Ilmumisaeg: 06-Jun-2016
  • Kirjastus: Newnes (an imprint of Butterworth-Heinemann Ltd )
  • Keel: eng
  • ISBN-13: 9780081006344
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Designer's Guide to the Cortex-M Processor FamilySuurem pilt
  • Formaat: PDF+DRM
  • Ilmumisaeg: 06-Jun-2016
  • Kirjastus: Newnes (an imprint of Butterworth-Heinemann Ltd )
  • Keel: eng
  • ISBN-13: 9780081006344
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The Designer’s Guide to the Cortex-M Microcontrollers gives you an easy-to-understand introduction to the concepts required to develop programs in C with a Cortex-M based microcontroller. The book begins with an overview of the Cortex-M family, giving architectural descriptions supported with practical examples, enabling you to easily develop basic C programs to run on the Cortex-M0/M0+/M3 and M4 and M7. It then examines the more advanced features of the Cortex architecture such as memory protection, operating modes, and dual stack operation.

Once a firm grounding in the Cortex-M processor has been established the book introduces the use of a small footprint RTOS and the CMSIS-DSP library. The book also examines techniques for software testing and code reuse specific to Cortex-M microcontrollers. With this book you will learn: the key differences between the Cortex-M0/M0+/M3 and M4 and M7; how to write C programs to run on Cortex-M based processors; how to make the best use of the CoreSight debug system; the Cortex-M operating modes and memory protection; advanced software techniques that can be used on Cortex-M microcontrollers; how to use a Real Time Operating System with Cortex-M devices; how to optimize DSP code for the Cortex-M4; and how to build real time DSP systems.

  • Includes an update to the latest version (5) of MDK-ARM, which introduces the concept of using software device packs and software components
  • Includes overviews of the new CMSIS specifications
  • Covers developing software with CMSIS-RTOS showing how to use RTOS in a real world design
  • Provides a new chapter on the Cortex-M7 architecture covering all the new features
  • Includes a new chapter covering test driven development for Cortex-M microcontrollers
  • Features a new chapter on creating software components with CMSIS-Pack and device abstraction with CMSIS-Driver
  • Features a new chapter providing an overview of the ARMv8-M architecture including the TrustZone hardware security model

Muu info

Choose the right ARM Cortex-M architecture for your application and learn how to program your applications in C
Foreword xvii
Preface xix
Acknowledgments xxi
Chapter 1 Introduction to the Cortex-M Processor Family 1(22)
Cortex Profiles
1(2)
Cortex-M3
3(4)
Advanced Architectural Features
7(3)
Cortex-MO
10(3)
Cortex-MO+
13(3)
Cortex-M4
16(2)
DSP Instructions
18(1)
Cortex-M7
19(2)
Conclusion
21(2)
Chapter 2 Developing Software for the Cortex-M Family 23(48)
Introduction
23(1)
Keil Microcontroller Development Kit
23(1)
Software Packs
24(1)
The Tutorial Exercises
24(1)
Installation
25(2)
Exercise 2.1 Building a First Program
27(1)
The Blinky Project
28(24)
Project Configuration
52(13)
Exercise 2.2 Hardware Debug
65(4)
Conclusion
69(2)
Chapter 3 Cortex-M Architecture 71(60)
Introduction
71(1)
Cortex-M Instruction Set
71(1)
Programmer's Model and CPU Registers
72(2)
Program Status Register
74(1)
Q Bit and Saturated Maths Instructions
75(1)
Interrupts and Multicycle Instructions
76(1)
Conditional Execution—If Then Blocks
76(2)
Exercise 3.1 Saturated Maths and Conditional Execution
78(6)
Cortex-M Memory Map and Busses
84(3)
Write Buffer
87(1)
Memory Barrier Instructions
87(1)
System Control Block
87(2)
Bit Manipulation
89(2)
Exercise 3.2 Bit Banding
91(1)
Dedicated Bit Manipulation Instructions
92(1)
SysTick Timer
93(1)
Nested Vector Interrupt Controller
94(1)
Operating Modes
94(1)
Interrupt Handling—Entry
95(1)
Interrupt Handling—Exit
96(1)
Interrupt Handling—Exit Important!
97(1)
Exercise 3.3 SysTick Interrupt
97(5)
Cortex-M Processor Exceptions
102(2)
Usage Fault
103(1)
Bus Fault
103(1)
Memory Manager Fault
104(1)
Hard Fault
104(1)
Enabling Fault Exceptions
104(1)
Priority and Preemption
104(2)
Groups and Subgroup
106(1)
Runtime Priority Control
107(1)
Exception Model
107(3)
NVIC Tail Chaining
108(1)
NVIC Late Arriving
109(1)
NVIC POP Preemption
110(1)
Exercise 3.3 Working with Multiple Interrupts
110(5)
Bootloader Support
115(1)
Exercise 3.4 Bootloader
116(5)
Power Management
121(5)
Entering Low-Power Modes
123(1)
Configuring the Low-Power Modes
123(1)
Exercise 3.3 Low-Power Modes
124(2)
Moving From the Cortex-M3
126(1)
Cortex-M4
127(1)
Cortex-MO
127(2)
Cortex-MO+
129(1)
Conclusion
130(1)
Chapter 4 Cortex Microcontroller Software Interface Standard 131(24)
Introduction
131(2)
CMSIS Specifications
133(1)
CMSIS-Core
134(1)
CMSIS-RTOS
134(1)
CMSIS-DSP
135(1)
CMSIS-Driver
135(1)
CMSIS-SVD and DAP
135(1)
CMSIS-Pack
136(1)
Foundations of CMSIS
136(1)
Coding Rules
137(1)
MISRA-C
137(2)
CMSIS-Core Structure
139(1)
Startup Code
140(1)
System Code
141(1)
Device Header File
141(2)
CMSIS-Core Header Files
143(1)
Interrupts and Exceptions
144(3)
Exercise 4.1 CMSIS and User Code Comparison
147(2)
CMSIS-Core Register Access
148(1)
CMSIS-Core CPU Intrinsic Instructions
149(1)
Exercise 4.2 Intrinsic Bit Manipulation
150(1)
CMSIS-SIMD Intrinsics
151(1)
CMSIS-Core Debug Functions
152(1)
Hardware Breakpoint
152(1)
Instrumentation Trace
152(1)
CMSIS-Core Functions for Corex-M7
153(1)
Conclusion
153(2)
Chapter 5 Advanced Architecture Features 155(34)
Introduction
155(1)
Cortex Processor Operating Modes
155(3)
Exercise 5.1 Stack Configuration
158(3)
Supervisor Call
161(2)
Exercise 5.2 Supervisor Call
163(3)
PEND_SV Exception
166(1)
Example Pend_SV
167(2)
Interprocessor Events
169(1)
Exclusive Access
169(3)
Exercise 5.4 Exclusive Access
172(1)
Memory Protection Unit
173(2)
Configuring the MPU
175(3)
Exercise 5.5 MPU Configuration
178(6)
MPU Subregions
184(1)
MPU Limitations
185(1)
AHB Lite Bus Interface
185(2)
Conclusion
187(2)
Chapter 6 Cortex-M7 Processor 189(28)
Superscalar Architecture
190(1)
Branch Prediction
191(1)
Exercise 6.1 Simple Loop
191(2)
Bus Structure
193(2)
Memory Hierarchy
195(2)
Exercise 6.2 Locating Code and Data into the TCM
197(2)
Cache Units
199(1)
Cache Operation
200(3)
Instruction Cache
203(1)
Exercise 6.3 Instruction Cache
203(1)
Data Cache
204(1)
Memory Barriers
205(1)
Exercise 6.4 Example Data Cache
206(1)
Memory Protection Unit and Cache Configuration
206(1)
Cache Policy
207(2)
Managing the Data Cache
209(1)
Switch Off the Cache
209(1)
Disable Caching over a Region of System Memory
209(1)
Change the Cache Policy for a Region of System Memory
209(1)
Use the Cache Management Functions to Guarantee Coherency
209(1)
Exercise 6.5 Data Cache Configuration
209(4)
Double Precision Floating Point Unit
213(1)
Functional Safety
214(1)
Cortex-M7 Safety Features
215(1)
Safety Documentation
215(1)
Development Tools
216(1)
Conclusion
216(1)
Chapter 7 Debugging with CoreSight 217(38)
Introduction
217(2)
CoreSight Hardware
219(1)
Debugger Hardware
220(1)
CoreSight Debug Architecture
221(1)
Exercise 7.1 CoreSight Debug
221(1)
Hardware Configuration
222(1)
Software Configuration
223(6)
Debug Limitations
229(1)
Instrumentation Trace
229(1)
Exercise 7.2 Setting Up the ITM
230(3)
System Control Block Debug Support
233(1)
Tracking Faults
234(1)
Exercise 7.3 Processor Fault Exceptions
235(4)
Instruction Trace with the Embedded Trace Macrocell
239(2)
Exercise 7.4 Using the ETM Trace
241(3)
CMSIS-DAP
244(1)
Cortex-M0+ MTB
245(1)
Exercise 7.5 Micro Trace Buffer
246(2)
CMSIS System Viewer Description
248(1)
Exercise 7.6 CMSIS-SVD
249(5)
Conclusion Debug Features Summary
254(1)
Chapter 8 Practical DSP for Cortex-M4 and Cortex-M7 255(38)
Introduction
255(1)
Hardware FPU
255(1)
FPU Integration
256(1)
FPU Registers
257(1)
Cortex-M7 FPU
258(1)
Enabling the FPU
258(1)
Exceptions and the FPU
258(1)
Using the FPU
259(1)
Exercise 8.1 Floating Point Unit
259(6)
Cortex-M4/M7 DSP and SIMD Instructions
265(4)
Exercise 8.2 SIMD Instructions
269(3)
Exercise 8.3 Optimizing DSP Algorithms
272(7)
The CMSIS-DSP Library
279(1)
CMSIS-DSP Library Functions
279(1)
Exercise 8.3 Using the CMSIS-DSP Library
280(5)
DSP Data Processing Techniques
285(1)
Exercise 8.4 FIR Filter with Block Processing
286(3)
Fixed Point DSP with Q Numbers
289(1)
Exercise 8.5 Fixed Point FFT Transform
290(2)
Conclusion
292(1)
Chapter 9 Cortex Microcontroller Software Interface Standard-Real-Time Operating System 293(58)
Introduction
293(1)
First Steps with CMSIS-RTOS
294(1)
Accessing the CMSIS-RTOS API
294(1)
Threads
295(1)
Starting the RTOS
296(1)
Exercise 9.1 A First CMSIS-RTOS Project
297(9)
Creating Threads
306(1)
Exercise 9.2 Creating and Managing Threads
307(3)
Thread Management and Priority
310(1)
Exercise 9.3 Creating and Managing Threads II
311(1)
Multiple Instances
312(1)
Exercise 9.4 Multiple Thread Instances
313(1)
Time Management
314(1)
Time Delay
314(1)
Waiting for an Event
315(1)
Exercise 9.5 Time Management
315(1)
Virtual Timers
316(1)
Exercise 9.6 Virtual Timer
317(2)
Sub-Millisecond Delays
319(1)
Idle Demon
319(1)
Exercise 9.7 Idle Thread
320(3)
Inter-Thread Communication
323(1)
Signals
323(1)
Exercise 9.8 Signals
324(1)
Semaphores
325(1)
Exercise 9.9 Semaphore Signaling
326(2)
Using Semaphores
328(1)
Signaling
328(1)
Multiplex
329(1)
Exercise 9.10 Multiplex
329(1)
Rendezvous
330(1)
Exercise 9.11 Rendezvous
330(1)
Barrier Turnstile
331(1)
Exercise 9.12 Semaphore Barrier
332(1)
Semaphore Caveats
332(1)
Mutex
333(1)
Exercise 9.13 Mutex
333(2)
Mutex Caveats
335(1)
Data Exchange
335(2)
Message Queue
337(1)
Exercise 9.14 Message Queue
338(1)
Memory Pool
339(1)
Exercise 9.15 Memory Pool
340(1)
Mail Queue
341(1)
Exercise 9.16 Mailbox
342(1)
Configuration
343(1)
Thread Definition
344(1)
Kernel Debug Support
344(2)
System Timer Configuration
346(1)
Timeslice Configuration
346(1)
Scheduling Options
346(2)
Preemptive Scheduling
347(1)
Round-Robin Scheduling
347(1)
Round-Robin Preemptive Scheduling
348(1)
Cooperative Multitasking
348(1)
RTX Source Code
348(1)
RTX License
349(1)
Conclusion
350(1)
Chapter 10 RTOS Techniques 351(36)
Introduction
351(1)
RTOS and Interrupts
351(1)
RTOS Interrupt Handling
352(2)
Exercise 10.1 RTOS Interrupt Exercise Handling
354(1)
User Supervisor Functions
355(1)
Exercise 10.2 RTOS and User SVC Exceptions
356(2)
Power Management
358(1)
Power Management First Steps
358(2)
Power Management Strategy
360(2)
Watchdog Management
362(1)
Integrating ISRs
363(1)
Exercise 10.3 Power and Watchdog Management
364(5)
Startup Barrier
369(1)
Designing for Real Time
370(5)
Buffering Techniques—The Double or Circular Buffer
370(1)
Buffering Techniques FIFO Message Queue
371(4)
Balancing the Load
375(1)
Exercise 10.4 RTX Real Time
375(5)
Shouldering the Load, the Direct Memory Access Controller
380(1)
Designing for Debug
381(1)
Exercise 10.5 Run-Time Diagnostics
382(3)
Conclusion
385(2)
Chapter 11 Test Driven Development 387(24)
Introduction
387(3)
The TDD Development Cycle
389(1)
Test Framework
389(1)
Test Automation
389(1)
Installing the Unity Framework
390(1)
Exercise 11.1 Test Driven Development
390(12)
Adding the Unity Test Framework
391(2)
Configuring the Project Build Targets
393(4)
Adding the Test Cases
397(2)
Automating the TDD Cycle
399(3)
Testing RTOS Threads
402(2)
Exercise 11.2 Testing RTOS Threads
404(3)
Decoupling Low Level Functions
405(1)
Testing Interrupts
406(1)
Exercise 11.3 Testing with Interrupts
407(2)
Conclusion
409(2)
Chapter 12 Software Components 411(34)
Introduction
411(1)
CMSIS Driver
412(7)
CMSIS Driver API
413(1)
Exercise 12.1 CMSIS-Driver
414(5)
Driver Validation
419(5)
Exercise 12.2 Driver Validation
419(5)
Designing a Software Component
424(3)
Exercise 12.3 GPS Component
424(3)
Creating a Software Pack
427(12)
Software Pack Structure
427(1)
Software Pack Utilities
428(11)
Configuration Wizard
439(4)
Exercise 12.4 Configuration Wizard
440(3)
Deploying Software Components
443(1)
Conclusion
444(1)
Chapter 13 ARMv8-M 445(12)
Introduction
445(1)
Common Architectural Enhancements
446(1)
ARMv8 Baseline Enhancements
446(1)
ARMv8-M Mainline Enhancements
447(1)
TrustZone
448(6)
Interrupts and Exceptions
451(3)
Software Development
454(1)
Compiler
454(1)
Real-Time Operating System
454(1)
Debugger
454(1)
Cortex Microcontroller Software Interface Standard
455(1)
Conclusion
455(2)
Appendix 457(4)
Index 461
Trevor Martin graduated from Brunel University in 1988 with an Honors degree in electrical and electronics engineering. In the same year, he began work as a junior hardware engineer at Philips Medical Systems. He joined Hitex in 1992 as a technical specialist for 8-bit microcontroller development tools. This included the 8051,68HC11\05\08 microcontrollers. He also gained experience with networking protocols such as CAN, USB, and TCP/IP. Since 2000, he has been supporting ARM-based microcontrollers, initially ARM7 and ARM9 CPU then moving to Cortex-M processor. To promote these devices, he has worked closely with both NXP and ST and also TI and Freescale to a lesser extent. Since 2005, he has written a number of Insiders Guide” books that are introductory tutorials to ARM-based microcontroller families such as LPC2000, STR9, and STM32. He also runs regular training courses, a general Cortex Microcontroller workshop and also device-specific courses.
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