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E-raamat: Digital Design and Computer Architecture, ARM Edition

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(Assistant Professor of Engineering, Harvey Mudd College, Claremont, CA, USA), (Associate Professor of Engineering, Harvey Mudd College, Claremont, CA, USA)
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  • Ilmumisaeg: 09-Apr-2015
  • Kirjastus: Morgan Kaufmann Publishers In
  • Keel: eng
  • ISBN-13: 9780128009116
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Digital Design and Computer Architecture, ARM EditionSuurem pilt
  • Formaat: PDF+DRM
  • Ilmumisaeg: 09-Apr-2015
  • Kirjastus: Morgan Kaufmann Publishers In
  • Keel: eng
  • ISBN-13: 9780128009116
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Digital Design and Computer Architecture: ARM Edition takes a unique and modern approach to digital design. Beginning with digital logic gates and progressing to the design of combinational and sequential circuits, Harris and Harris use these fundamental building blocks as the basis for what follows: the design of an actual ARM processor. With over 75% of the world’s population using products with ARM processors, the design of the ARM processor offers an exciting and timely application of digital design while also teaching the fundamentals of computer architecture. SystemVerilog and VHDL are integrated throughout the text in examples illustrating the methods and techniques for CAD-based circuit design. By the end of this book, readers will be able to build their own microprocessor and will have a top-to-bottom understanding of how it works. Harris and Harris have combined an engaging and humorous writing style with an updated and hands-on approach to digital design.
  • Covers the fundamentals of digital logic design and reinforces logic concepts through the design of an ARM microprocessor.

  • Features side-by-side examples of the two most prominent Hardware Description Languages (HDLs)-SystemVerilog and VHDL-which illustrate and compare the ways each can be used in the design of digital systems.

  • Includes examples throughout the text that enhance the reader’s understanding and retention of key concepts and techniques.

  • The Companion website includes a chapter on I/O systems with practical examples that show how to use the Raspberry Pi computer to communicate with peripheral devices such as LCDs, Bluetooth radios, and motors.

  • The Companion website also includes appendices covering practical digital design issues and C programming as well as links to CAD tools, lecture slides, laboratory projects, and solutions to exercises.

Arvustused

"...this excellent book covers a wide spectrum of digital design and computer architecture and organizationa necessary book for many digital design enthusiasts in the years to come." --Computing Reviews

Muu info

Takes the reader from the fundamentals of digital logic to the actual design of an ARM processor
Preface xix
Features xx
Online Supplements xxi
How to Use the Software Tools in a Course xxii
Labs xxii
Bugs xxiii
Acknowledgments xxiv
Chapter 1 From Zero to One
3(52)
1.1 The Game Plan
3(1)
1.2 The Art of Managing Complexity
4(3)
1.2.1 Abstraction
4(1)
1.2.2 Discipline
5(1)
1.2.3 The Three-Y's
6(1)
1.3 The Digital Abstraction
7(2)
1.4 Number Systems
9(10)
1.4.1 Decimal Numbers
9(1)
1.4.2 Binary Numbers
9(2)
1.4.3 Hexadecimal Numbers
11(2)
1.4.4 Bytes, Nibbles, and All That Jazz
13(1)
1.4.5 Binary Addition
14(1)
1.4.6 Signed Binary Numbers
15(4)
1.5 Logic Gates
19(3)
1.5.1 NOT Gate
20(1)
1.5.2 Buffer
20(1)
1.5.3 AND Gate
20(1)
1.5.4 OR Gate
21(1)
1.5.5 Other Two-Input Gates
21(1)
1.5.6 Multiple-Input Gates
21(1)
1.6 Beneath the Digital Abstraction
22(4)
1.6.1 Supply Voltage
22(1)
1.6.2 Logic Levels
22(1)
1.6.3 Noise Margins
23(1)
1.6.4 DC Transfer Characteristics
24(1)
1.6.5 The Static Discipline
24(2)
1.7 CMOS Transistors
26(8)
1.7.1 Semiconductors
27(1)
1.7.2 Diodes
27(1)
1.7.3 Capacitors
28(1)
1.7.4 nMOS and pMOS Transistors
28(3)
1.7.5 CMOS NOT Gate
31(1)
1.7.6 Other CMOS Logic Gates
31(2)
1.7.7 Transmission Gates
33(1)
1.7.8 Pseudo-nMOS Logic
33(1)
1.8 Power Consumption
34(1)
1.9 Summary and a Look Ahead
35(20)
Exercises
37(15)
Interview Questions
52(3)
Chapter 2 Combinational Logic Design
55(54)
2.1 Introduction
55(3)
2.2 Boolean Equations
58(2)
2.2.1 Terminology
58(1)
2.2.2 Sum-of-Products Form
58(2)
2.2.3 Product-of-Sums Form
60(1)
2.3 Boolean Algebra
60(6)
2.3.1 Axioms
61(1)
2.3.2 Theorems of One Variable
61(1)
2.3.3 Theorems of Several Variables
62(2)
2.3.4 The Truth Behind It All
64(1)
2.3.5 Simplifying Equations
65(1)
2.4 From Logic to Gates
66(3)
2.5 Multilevel Combinational Logic
69(4)
2.5.1 Hardware Reduction
70(1)
2.5.2 Bubble Pushing
71(2)
2.6 X's and Z's, Oh My
73(2)
2.6.1 Illegal Value: X
73(1)
2.6.2 Floating Value: Z
74(1)
2.7 Karnaugh Maps
75(8)
2.7.1 Circular Thinking
76(1)
2.7.2 Logic Minimization with K-Maps
77(4)
2.7.3 Don't Cares
81(1)
2.7.4 The Big Picture
82(1)
2.8 Combinational Building Blocks
83(5)
2.8.1 Multiplexers
83(3)
2.8.2 Decoders
86(2)
2.9 Timing
88(7)
2.9.1 Propagation and Contamination Delay
88(4)
2.9.2 Glitches
92(3)
2.10 Summary
95(14)
Exercises
97(9)
Interview Questions
106(3)
Chapter 3 Sequential Logic Design
109(64)
3.1 Introduction
109(1)
3.2 Latches and Flip-Flops
109(10)
3.2.1 SR Latch
111(2)
3.2.2 D Latch
113(1)
3.2.3 D Flip-Flop
114(1)
3.2.4 Register
114(1)
3.2.5 Enabled Flip-Flop
115(1)
3.2.6 Resettable Flip-Flop
116(1)
3.2.7 Transistor-Level Latch and Flip-Flop Designs
116(2)
3.2.8 Putting It All Together
118(1)
3.3 Synchronous Logic Design
119(4)
3.3.1 Some Problematic Circuits
119(1)
3.3.2 Synchronous Sequential Circuits
120(2)
3.3.3 Synchronous and Asynchronous Circuits
122(1)
3.4 Finite State Machines
123(18)
3.4.1 FSM Design Example
123(6)
3.4.2 State Encodings
129(3)
3.4.3 Moore and Mealy Machines
132(2)
3.4.4 Factoring State Machines
134(3)
3.4.5 Deriving an FSM from a Schematic
137(3)
3.4.6 FSM Review
140(1)
3.5 Timing of Sequential Logic
141(16)
3.5.1 The Dynamic Discipline
142(1)
3.5.2 System Timing
142(6)
3.5.3 Clock Skew
148(3)
3.5.4 Metastability
151(1)
3.5.5 Synchronizers
152(2)
3.5.6 Derivation of Resolution Time
154(3)
3.6 Parallelism
157(4)
3.7 Summary
161(12)
Exercises
162(9)
Interview Questions
171(2)
Chapter 4 Hardware Description Languages
173(66)
4.1 Introduction
173(4)
4.1.1 Modules
173(1)
4.1.2 Language Origins
174(1)
4.1.3 Simulation and Synthesis
175(2)
4.2 Combinational Logic
177(13)
4.2.1 Bitwise Operators
177(3)
4.2.2 Comments and White Space
180(1)
4.2.3 Reduction Operators
180(1)
4.2.4 Conditional Assignment
181(1)
4.2.5 Internal Variables
182(2)
4.2.6 Precedence
184(1)
4.2.7 Numbers
185(1)
4.2.8 Z's and X's
186(2)
4.2.9 Bit Swizzling
188(1)
4.2.10 Delays
188(2)
4.3 Structural Modeling
190(3)
4.4 Sequential Logic
193(5)
4.4.1 Registers
193(1)
4.4.2 Resettable Registers
194(2)
4.4.3 Enabled Registers
196(1)
4.4.4 Multiple Registers
197(1)
4.4.5 Latches
198(1)
4.5 More Combinational Logic
198(11)
4.5.1 Case Statements
201(1)
4.5.2 If Statements
202(3)
4.5.3 Truth Tables with Don't Cares
205(1)
4.5.4 Blocking and Nonblocking Assignments
205(4)
4.6 Finite State Machines
209(4)
4.7 Data Types
213(4)
4.7.1 SystemVerilog
214(1)
4.7.2 VHDL
215(2)
4.8 Parameterized Modules
217(3)
4.9 Testbenches
220(4)
4.10 Summary
224(15)
Exercises
226(11)
Interview Questions
237(2)
Chapter 5 Digital Building Blocks
239(56)
5.1 Introduction
239(1)
5.2 Arithmetic Circuits
239(16)
5.2.1 Addition
239(7)
5.2.2 Subtraction
246(1)
5.2.3 Comparators
246(2)
5.2.4 ALU
248(3)
5.2.5 Shifters and Rotators
251(1)
5.2.6 Multiplication
252(2)
5.2.7 Division
254(1)
5.2.8 Further Reading
255(1)
5.3 Number Systems
255(4)
5.3.1 Fixed-Point Number Systems
255(1)
5.3.2 Floating-Point Number Systems
256(3)
5.4 Sequential Building Blocks
259(5)
5.4.1 Counters
260(1)
5.4.2 Shift Registers
261(3)
5.5 Memory Arrays
264(7)
5.5.1 Overview
264(2)
5.5.2 Dynamic Random Access Memory (DRAM)
266(1)
5.5.3 Static Random Access Memory (SRAM)
267(1)
5.5.4 Area and Delay
267(1)
5.5.5 Register Files
268(1)
5.5.6 Read Only Memory
268(2)
5.5.7 Logic Using Memory Arrays
270(1)
5.5.8 Memory HDL
271(1)
5.6 Logic Arrays
271(10)
5.6.1 Programmable Logic Array
272(2)
5.6.2 Field Programmable Gate Array
274(5)
5.6.3 Array Implementations
279(2)
5.7 Summary
281(14)
Exercises
282(11)
Interview Questions
293(2)
Chapter 6 Architecture
295(90)
6.1 Introduction
295(1)
6.2 Assembly Language
296(7)
6.2.1 Instructions
297(1)
6.2.2 Operands: Registers, Memory, and Constants
298(5)
6.3 Programming
303(26)
6.3.1 Data-processing Instructions
303(3)
6.3.2 Condition Flags
306(2)
6.3.3 Branching
308(1)
6.3.4 Conditional Statements
309(3)
6.3.5 Getting Loopy
312(1)
6.3.6 Memory
313(4)
6.3.7 Function Calls
317(12)
6.4 Machine Language
329(10)
6.4.1 Data-processing Instructions
329(4)
6.4.2 Memory Instructions
333(1)
6.4.3 Branch Instructions
334(2)
6.4.4 Addressing Modes
336(1)
6.4.5 Interpreting Machine Language Code
336(1)
6.4.6 The Power of the Stored Program
337(2)
6.5 Lights, Camera, Action: Compiling, Assembling, and Loading
339(6)
6.5.1 The Memory Map
339(1)
6.5.2 Compilation
340(2)
6.5.3 Assembling
342(1)
6.5.4 Linking
343(1)
6.5.5 Loading
344(1)
6.6 Odds and Ends
345(5)
6.6.1 Loading Literals
345(1)
6.6.2 NOP
346(1)
6.6.3 Exceptions
347(3)
6.7 Evolution of ARM Architecture
350(10)
6.7.1 Thumb Instruction Set
351(1)
6.7.2 DSP Instructions
352(5)
6.7.3 Floating-Point Instructions
357(1)
6.7.4 Power-Saving and Security Instructions
358(1)
6.7.5 SIMD Instructions
358(2)
6.7.6 64-bit Architecture
360(1)
6.8 Another Perspective: x86 Architecture
360(8)
6.8.1 x86 Registers
362(1)
6.8.2 x86 Operands
362(1)
6.8.3 Status Flags
363(1)
6.8.4 x86 Instructions
364(1)
6.8.5 x86 Instruction Encoding
364(3)
6.8.6 Other x86 Peculiarities
367(1)
6.8.7 The Big Picture
368(1)
6.9 Summary
368(17)
Exercises
370(13)
Interview Questions
383(2)
Chapter 7 Microarchitecture
385(102)
7.1 Introduction
385(4)
7.1.1 Architectural State and Instruction Set
385(1)
7.1.2 Design Process
386(2)
7.1.3 Microarchitectures
388(1)
7.2 Performance Analysis
389(1)
7.3 Single-Cycle Processor
390(16)
7.3.1 Single-Cycle Datapath
390(7)
7.3.2 Single-Cycle Control
397(5)
7.3.3 More Instructions
402(1)
7.3.4 Performance Analysis
402(4)
7.4 Multicycle Processor
406(19)
7.4.1 Multicycle Datapath
407(6)
7.4.2 Multicycle Control
413(8)
7.4.3 Performance Analysis
421(4)
7.5 Pipelined Processor
425(18)
7.5.1 Pipelined Datapath
428(2)
7.5.2 Pipelined Control
430(1)
7.5.3 Hazards
431(10)
7.5.4 Performance Analysis
441(2)
7.6 HDL Representation
443(13)
7.6.1 Single-Cycle Processor
444(5)
7.6.2 Generic Building Blocks
449(3)
7.6.3 Testbench
452(4)
7.7 Advanced Microarchitecture
456(14)
7.7.1 Deep Pipelines
457(1)
7.7.2 Micro-Operations
458(1)
7.7.3 Branch Prediction
459(2)
7.7.4 Superscalar Processor
461(2)
7.7.5 Out-of-Order Processor
463(2)
7.7.6 Register Renaming
465(2)
7.7.7 Multithreading
467(1)
7.7.8 Multiprocessors
468(2)
7.8 Real-World Perspective: Evolution of ARM Microarchitecture
470(6)
7.9 Summary
476(11)
Exercises
478(6)
Interview Questions
484(3)
Chapter 8 Memory Systems
487(44)
8.1 Introduction
487(4)
8.2 Memory System Performance Analysis
491(1)
8.3 Caches
492(16)
8.3.1 What Data is Held in the Cache?
493(1)
8.3.2 How is Data Found?
494(8)
8.3.3 What Data is Replaced?
502(1)
8.3.4 Advanced Cache Design
503(4)
8.3.5 The Evolution of ARM Caches
507(1)
8.4 Virtual Memory
508(10)
8.4.1 Address Translation
510(2)
8.4.2 The Page Table
512(2)
8.4.3 The Translation Lookaside Buffer
514(1)
8.4.4 Memory Protection
515(1)
8.4.5 Replacement Policies
516(1)
8.4.6 Multilevel Page Tables
516(2)
8.5 Summary
518(13)
Epilogue
519(1)
Exercises
520(9)
Interview Questions
529(2)
Chapter 9 I/O Systems
531(2)
9.1 Introduction
531(1)
Chapter 9 Is available as an online supplement
531(1)
9.1 Introduction
531(1)
9.2 Memory-Mapped I/O
531(1)
9.3 Embedded I/O Systems
531(1)
9.3.1 BCM2835 System-on-Chip
531(1)
9.3.2 Device Drivers
531(1)
9.3.3 General-Purpose Digital I/O
531(1)
9.3.4 Serial I/O
531(1)
9.3.5 Timers
531(1)
9.3.6 Analog I/O
531(1)
9.3.7 Interrupts
531(1)
9.4 Other Microcontroller Peripherals
531(1)
9.4.1 Character LCDs
531(1)
9.4.2 VGA Monitor
531(1)
9.4.3 Bluetooth Wireless Communication
531(1)
9.4.4 Motor Control
531(1)
9.5 Bus Interfaces
531(1)
9.5.1 AHB-Lite
531(1)
9.5.2 Memory and Peripheral Interface Example
531(1)
9.6 PC I/O Systems
531(1)
9.6.1 USB
531(1)
9.6.2 PCI and PCI Express
531(1)
9.6.3 DDR3 Memory
531(1)
9.6.4 Networking
531(1)
9.6.5 SATA
531(1)
9.6.6 Interfacing to a PC
531(1)
9.7 Summary
531(2)
Appendix A Digital System Implementation
533(2)
A.1 Introduction
533(1)
Appendix A Is available as an online supplement
533(1)
A.1 Introduction
533(1)
A.2 74xx Logic
533(1)
A.2.1 Logic Gates
533(1)
A.2.2 Other Functions
533(1)
A.3 Programmable Logic
533(1)
A.3.1 PROMs
533(1)
A.3.2 PLAs
533(1)
A.3.3 FPGAs
533(1)
A.4 Application-Specific Integrated Circuits
533(1)
A.5 Data Sheets
533(1)
A.6 Logic Families
533(1)
A.7 Packaging and Assembly
533(1)
A.8 Transmission Lines
533(1)
A.8.1 Matched Termination
533(1)
A.8.2 Open Termination
533(1)
A.8.3 Short Termination
533(1)
A.8.4 Mismatched Termination
533(1)
A.8.5 When to Use Transmission Line Models
533(1)
A.8.6 Proper Transmission Line Terminations
533(1)
A.8.7 Derivation of Z0
533(1)
A.8.8 Derivation of the Reflection Coefficient
533(1)
A.8.9 Putting It All Together
533(1)
A.9 Economics
533(2)
Appendix B ARM Instructions
535(6)
B.1 Data-Processing Instructions
535(3)
B.1.1 Multiply Instructions
537(1)
B.2 Memory Instructions
538(1)
B.3 Branch Instructions
539(1)
B.4 Miscellaneous Instructions
539(1)
B.5 Condition Flags
540(1)
Appendix C C Programming
541(2)
C.1 Introduction
541(1)
Appendix C Is available as an online supplement
541(1)
C.1 Introduction
541(1)
C.2 Welcome to C
541(1)
C.2.1 C Program Dissection
541(1)
C.2.2 Running a C Program
541(1)
C.3 Compilation
541(1)
C.3.1 Comments
541(1)
C.3.2 #define
541(1)
C.3.3 #include
541(1)
C.4 Variables
541(1)
C.4.1 Primitive Data Types
541(1)
C.4.2 Global and Local Variables
541(1)
C.4.3 Initializing Variables
541(1)
C.5 Operators
541(1)
C.6 Function Calls
541(1)
C.7 Control-Flow Statements
541(1)
C.7.1 Conditional Statements
541(1)
C.7.2 Loops
541(1)
C.8 More Data Types
541(1)
C.8.1 Pointers
541(1)
C.8.2 Arrays
541(1)
C.8.3 Characters
541(1)
C.8.4 Strings
541(1)
C.8.5 Structures
541(1)
C.8.6 typedef
541(1)
C.8.7 Dynamic Memory Allocation
541(1)
C.8.8 Linked Lists
541(1)
C.9 Standard Libraries
541(1)
C.9.1 stdio
541(1)
C.9.2 stdlib
541(1)
C.9.3 math
541(1)
C.9.4 string
541(1)
C.10 Compiler and Command Line Options
541(1)
C.10.1 Compiling Multiple C Source Files
541(1)
C.10.2 Compiler Options
541(1)
C.10.3 Command Line Arguments
541(1)
C.11 Common Mistakes
541(2)
Index 543
Sarah L. Harris is an Assistant Professor of Engineering at Harvey Mudd College. She received her Ph.D. and M.S. in Electrical Engineering from Stanford University. Before attending Stanford, she received a B.S. in Electrical and Computer Engineering from Brigham Young University. Sarah has also worked with Hewlett-Packard, the San Diego Supercomputer Center, Nvidia, and Microsoft Research in Beijing. Sarah loves teaching, exploring and developing new technologies, traveling, wind surfing, rock climbing, and playing the guitar. Her recent exploits include researching sketching interfaces for digital circuit design, acting as a science correspondent for a National Public Radio affiliate, and learning how to kite surf. She speaks four languages and looks forward to learning more in the near future. David Harris is the Harvey S. Mudd Professor of Engineering Design at Harvey Mudd College. He received his Ph.D. in electrical engineering from Stanford University and his M.Eng. in electrical engineering and computer science from MIT. Before attending Stanford, he worked at Intel as a logic and circuit designer on the Itanium and Pentium II processors. Since then, he has consulted at Sun Microsystems, Hewlett-Packard, Broadcom, and other design companies. David holds more than a dozen patents and is the author of three other textbooks on chip design, as well as many Southern California hiking guidebooks. When he is not working, he enjoys hiking, flying, and making things with his three sons.
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