Preface |
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ix | |
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1 | (48) |
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1 | (1) |
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1 | (1) |
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2 | (2) |
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4 | (1) |
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1.5 Hexadecimal numeration |
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5 | (1) |
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1.6 Representation in a radix B |
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6 | (1) |
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1.7 Binary-coded decimal numbers |
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7 | (1) |
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1.8 Representations of signed integers |
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8 | (5) |
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1.8.1 Sign-magnitude representation |
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9 | (1) |
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1.8.2 Two's complement representation |
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10 | (2) |
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1.8.3 Excess-E representation |
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12 | (1) |
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1.9 Representation of the fractional part of a number |
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13 | (3) |
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1.10 Arithmetic operations on binary numbers |
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16 | (4) |
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16 | (1) |
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17 | (1) |
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18 | (1) |
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19 | (1) |
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1.11 Representation of real numbers |
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20 | (8) |
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1.11.1 Fixed-point representation |
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20 | (2) |
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1.11.2 Floating-point representation |
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22 | (6) |
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28 | (3) |
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28 | (1) |
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29 | (2) |
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31 | (1) |
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31 | (1) |
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1.13 Codes to protect against errors |
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31 | (5) |
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31 | (2) |
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1.13.2 Error correcting codes |
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33 | (3) |
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36 | (2) |
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38 | (11) |
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49 | (66) |
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49 | (1) |
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50 | (4) |
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51 | (1) |
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51 | (1) |
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52 | (1) |
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52 | (1) |
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2.2.5 Complementary logic gates |
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53 | (1) |
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54 | (1) |
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54 | (1) |
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2.5 The correspondence between a truth table and a logic function |
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55 | (2) |
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57 | (19) |
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2.6.1 Boolean algebra theorems |
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59 | (6) |
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65 | (8) |
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2.6.3 Simplification of logic functions with multiple outputs |
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73 | (1) |
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2.6.4 Factorization of logic functions |
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74 | (2) |
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2.7 Multi-level logic circuit implementation |
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76 | (13) |
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77 | (1) |
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2.7.2 NAND gate logic circuit |
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78 | (2) |
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2.7.3 NOR gate based logic circuit |
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80 | (2) |
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2.7.4 Representation based on XOR and AND operators |
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82 | (7) |
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2.8 Practical considerations |
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89 | (4) |
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2.8.1 Timing diagram for a logic circuit |
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90 | (1) |
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90 | (2) |
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92 | (1) |
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2.9 Demonstration of some Boolean algebra identities |
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93 | (4) |
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97 | (4) |
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101 | (14) |
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Chapter 3 Function Blocks of Combinational Logic |
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115 | (88) |
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115 | (1) |
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115 | (6) |
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3.3 Demultiplexer and decoder |
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121 | (6) |
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3.4 Implementation of logic functions using multiplexers or decoders |
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127 | (3) |
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127 | (2) |
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129 | (1) |
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130 | (13) |
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131 | (3) |
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134 | (2) |
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136 | (7) |
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143 | (12) |
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3.6.1 Binary code and Gray code |
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143 | (6) |
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3.6.2 BCD and excess-3 code |
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149 | (6) |
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3.7 Parity check generator |
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155 | (5) |
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160 | (5) |
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165 | (8) |
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173 | (30) |
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Chapter 4 Systematic Methods for the Simplification of Logic Functions |
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203 | (54) |
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203 | (1) |
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4.2 Definitions and reminders |
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203 | (2) |
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204 | (1) |
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4.2.2 Minimization principle of a logic function |
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204 | (1) |
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205 | (15) |
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4.3.1 Function of five variables |
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205 | (2) |
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4.3.2 Function of six variables |
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207 | (1) |
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4.3.3 Karnaugh map with entered variable |
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208 | (7) |
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215 | (5) |
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4.3.5 Representation based on the XOR and AND operators |
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220 | (1) |
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4.4 Systematic methods for simplification |
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220 | (21) |
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4.4.1 Determination of prime implicants |
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221 | (3) |
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4.4.2 Finding the constitutive terms of a minimal expression |
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224 | (11) |
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4.4.3 Quine--McCluskey technique: simplification of incompletely defined functions |
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235 | (1) |
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4.4.4 Simplification of functions with multiple outputs |
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235 | (6) |
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241 | (2) |
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243 | (14) |
Bibliography |
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257 | (2) |
Index |
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259 | |