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E-raamat: Digital Integrated Circuits: Design-for-Test Using Simulink and Stateflow

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  • Formaat: 320 pages
  • Ilmumisaeg: 03-Oct-2018
  • Kirjastus: CRC Press Inc
  • Keel: eng
  • ISBN-13: 9781351838009
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Digital Integrated Circuits: Design-for-Test Using Simulink and StateflowSuurem pilt
  • Formaat: 320 pages
  • Ilmumisaeg: 03-Oct-2018
  • Kirjastus: CRC Press Inc
  • Keel: eng
  • ISBN-13: 9781351838009
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As part of the tendency to integrate the MATLAB system, especially its two components Simulink and Stateflow, into the process of modern digital design, Perelroyzen explains how to construct Simulink models for digital project test benches in the field of design-for-test. After describing Simulink and Stateflow, he discusses Simulink model building for fault modeling and simulation for combinational circuits and sequential circuits. All the software is proprietary. Annotation ©2007 Book News, Inc., Portland, OR (booknews.com)

A current trend in digital design-the integration of the MATLAB® components Simulink® and Stateflow® for model building, simulations, system testing, and fault detection-allows for better control over the design flow process and, ultimately, for better system results. Digital Integrated Circuits: Design-for-Test Using Simulink® and Stateflow® illustrates the construction of Simulink models for digital project test benches in certain design-for-test fields.

The first two chapters of the book describe the major tools used for design-for-test. The author explains the process of Simulink model building, presents the main library blocks of Simulink, and examines the development of finite-state machine modeling using Stateflow diagrams. Subsequent chapters provide examples of Simulink modeling and simulation for the latest design-for-test fields, including combinational and sequential circuits, controllability, and observability; deterministic algorithms; digital circuit dynamics; timing verification; built-in self-test (BIST) architecture; scan cell operations; and functional and diagnostic testing. The book also discusses the automatic test pattern generation (ATPG) process, the logical determinant theory, and joint test action group (JTAG) interface models.

Digital Integrated Circuits explores the possibilities of MATLAB's tools in the development of application-specific integrated circuit (ASIC) design systems. The book shows how to incorporate Simulink and Stateflow into the process of modern digital design.
Chapter 1 Simulink®: Dynamic System Simulation for MATLAB® 1(64)
1.1 Introduction
1(2)
1.1.1 Hierarchical Systems
1(11)
1.1.1.1 Blocks and Connections: Various Approaches
2(1)
1.1.1.2 Oriented Blocks and Connections
2(1)
1.1.1.3 Description of Hybrid Systems
3(1)
1.2 Creating a Model
3(7)
1.3 Running a Simulation
10(1)
1.4 Analyzing Simulation Results
10(1)
1.5 Subsystems: Using Masks to Customize Blocks
11(1)
1.6 Reference Blocks
12(44)
1.6.1 Continuous Library
12(1)
1.6.1.1 Transport Delay Block
12(1)
1.6.1.2 Variable Transport Delay Block
12(1)
1.6.2 Discrete Library
12(2)
1.6.2.1 Discrete Filter Block
12(2)
1.6.2.2 Discrete-Time Integrator Block
14(1)
1.6.2.3 Discrete State-Space Block
14(1)
1.6.2.4 Discrete Transfer Fcn Block
14(1)
1.6.2.5 Unit Delay Block
14(1)
1.6.3 Discontinuities Library
14(1)
1.6.3.1 Hit Crossing Block
15(1)
1.6.4 Link for ModelSim Library
15(1)
1.6.4.1 The VHDL Cosimulation, VHDL Sink, VHDL Source, and To VCD File Blocks
15(1)
1.6.5 Look-Up Tables
15(3)
1.6.5.1 Direct Look-Up Table (n-D) Block
17(1)
1.6.5.2 Look-Up Table (2-D) Block
17(1)
1.6.5.3 Look-Up Table (n-D) Block
18(1)
1.6.6 Math Operations Library
18(7)
1.6.6.1 Bitwise Logical Operator Block
20(1)
1.6.6.2 Combinatorial Logic Block
20(1)
1.6.6.3 Gain Block
21(1)
1.6.6.4 Logical Operator Block
21(1)
1.6.6.5 Matrix Gain Block
22(1)
1.6.6.6 MinMax Block
22(1)
1.6.6.7 Product Block
23(1)
1.6.6.8 Relational Operator Block
24(1)
1.6.6.9 Sum Block
24(1)
1.6.7 Ports&Subsystems Library
25(5)
1.6.7.1 Atomic Subsystem Block
25(1)
1.6.7.2 Enabled Subsystem Block
25(1)
1.6.7.3 Enabled and Triggered Subsystem Block
26(1)
1.6.7.4 For Iterator Subsystem Block
26(1)
1.6.7.5 Function-Call Generator Block
27(1)
1.6.7.6 Function-Call Subsystem Block
27(1)
1.6.7.7 If Action Subsystem Block
27(1)
1.6.7.8 Subsystem Block
27(1)
1.6.7.9 Subsystem Examples Block
27(1)
1.6.7.10 Triggered Subsystem Block
27(1)
1.6.7.11 Switch Case Block
28(1)
1.6.7.12 Switch Case Action Subsystem Block
28(1)
1.6.7.13 While Iterator Subsystem Block
29(1)
1.6.8 Signal Attributes Library
30(3)
1.6.8.1 Data Type Conversion Block
30(1)
1.6.8.2 IC Block
31(1)
1.6.8.3 Probe Block
31(1)
1.6.8.4 Rate Transition Block
32(1)
1.6.8.5 Signal Specification Block
33(1)
1.6.8.6 Width Block
33(1)
1.6.9 Signal Routing Library
33(6)
1.6.9.1 Bus Creator Block
34(1)
1.6.9.2 Bus Selector Block
34(1)
1.6.9.3 Data Store Block
34(1)
1.6.9.4 Demux Block
35(1)
1.6.9.5 From Block
35(2)
1.6.9.6 Goto Block
37(1)
1.6.9.7 Manual Switch Block
37(1)
1.6.9.8 Multiport Switch Block
37(2)
1.6.9.9 Mux Block
39(1)
1.6.9.10 Selector Block
39(1)
1.6.9.11 Switch Block
39(1)
1.6.10 Simulink Extras Library
39(3)
1.6.10.1 Clock Block
39(1)
1.6.10.2 DFF Block
40(1)
1.6.10.3 D Latch Block
40(2)
1.6.10.4 JKFF Block
42(1)
1.6.10.5 SRFF Block
42(1)
1.6.11 Sinks Library
42(4)
1.6.11.1 Display Block
42(1)
1.6.11.2 Floating Scope Block
42(1)
1.6.11.3 Out1 Block
43(1)
1.6.11.4 Scope Block
43(1)
1.6.11.5 Stop Simulation Block
43(1)
1.6.11.6 Terminator Block
44(2)
1.6.11.7 To File Block
46(1)
1.6.11.8 To Workspace Block
46(1)
1.6.12 Sources Library
46(4)
1.6.12.1 Constant Block
47(1)
1.6.12.2 Digital Clock Block
47(1)
1.6.12.3 Inl Block
47(1)
1.6.12.4 From File Block
47(1)
1.6.12.5 From Workspace Block
47(1)
1.6.12.6 Pulse Generator Block
48(1)
1.6.12.7 Signal Builder Block
48(1)
1.6.12.8 Signal Generator Block
48(2)
1.6.12.9 Step Block
50(1)
1.6.13 Stateflow Library
50(1)
1.6.13.1 Chart Block
50(1)
1.6.14 User-Defined Functions Library
51(3)
1.6.14.1 Fcn Block
51(1)
1.6.14.2 MATLAB Fcn Block
51(1)
1.6.14.3 S-Function Block
51(1)
1.6.14.4 S-Function Builder Block
51(3)
1.6.15 Additional Libraries
54(2)
1.7 Simulink Debugger
56(8)
References
64(1)
Chapter 2 Stateflow®: Creating Finite State Machine Models 65(28)
2.1 Introduction
65(2)
2.2 Creating Charts
67(5)
2.3 Entering a Stateflow Diagram
72(5)
2.3.1 Internal States
72(1)
2.3.2 Transitions
73(1)
2.3.3 Connective Junctions
74(1)
2.3.4 Default Transitions
74(2)
2.3.5 History Junctions
76(1)
2.4 Defining Events and Data
77(2)
2.5 Defining Stateflow Interfaces
79(1)
2.5.1 Inputs
79(1)
2.5.2 Outputs
79(1)
2.6 Exploring and Searching
79(2)
2.7 Debugging
81(10)
References
91(2)
Chapter 3 Fault Modeling and Simulation 93(50)
3.1 Fault Modeling
93(5)
3.1.1 Fault Models for Combinational Circuits
93(1)
3.1.2 Fault Models for Sequential Circuits
94(4)
3.2 Fault Simulation
98(44)
3.2.1 Fault Simulation for Combinational Circuits
98(14)
3.2.1.1 Cone and Test Vector Generation
105(4)
3.2.1.2 Partitioning Circuits into Cones and Subcones Using Simulink
109(3)
3.2.2 Fault Simulation for Sequential Circuits
112(30)
References
142(1)
Chapter 4 Testability Analysis Methods 143(30)
4.1 Combinational Controllability and Observability Analysis Models
143(21)
4.1.1 The AND Gate
144(1)
4.1.2 The NAND Gate
145(3)
4.1.3 The OR Gate
148(2)
4.1.4 The NOR Gate
150(1)
4.1.5 The XOR Gate
151(2)
4.1.6 The NXOR Gate
153(2)
4.1.7 The NOT Gate
155(9)
4.2 Sequential Controllability and Observability Analysis Models
164(8)
References
172(1)
Chapter 5 The Automatic Test Pattern Generation (ATPG) Process 173(22)
5.1 ATPG Fundamentals
173(10)
5.2 Combinational Circuit ATPG (Current-Based ATPG Algorithms for Combinational Circuits)
183(10)
5.2.1 The D-Algorithm Model
183(7)
5.2.2 The PODEM-Algorithm Model
190(3)
References
193(2)
Chapter 6 Timing Verification 195(66)
6.1 Logical Determinant Theory
195(9)
6.1.1 Infinite-Valued Logic
195(2)
6.1.2 The IVL Equations and Inequalities
197(1)
6.1.3 Order Logic and Logical Determinants
198(6)
6.1.4 Exposure of Large LDs
204(1)
6.1.5 Probabilistic Calculations in IVL
204(1)
6.2 Digital Circuit Dynamics
204(36)
6.2.1 Statistical and Dynamical Analysis of Combinational Circuits
204(2)
6.2.2 Switching Dynamic Processes in the System
206(10)
6.2.3 Dynamical Processes in Multi-Input Gates Following Arbitrary Length Impacts
216(9)
6.2.4 Logical Determinants and Sorting
225(15)
6.3 Model Building for Timing Verification
240(20)
6.3.1 Spectrum Analysis of a Switching Process
240(15)
6.3.2 The Comparison Model for Two Switching Processes
255(5)
References
260(1)
Chapter 7 System and Embedded Core Testing 261(52)
7.1 Introduction
261(1)
7.2 Scan Path Architectures and Techniques
261(21)
7.2.1 Models for BIST Architecture
261(14)
7.2.1.1 Signature Analysis
262(1)
7.2.1.2 LFSR Models
262(13)
7.2.2 Scan Cell Operations
275(7)
7.2.2.1 Built-In Logic Block Observer (BILBO) Register Model
280(2)
7.3 System and Embedded Core Testing
282(30)
7.3.1 Functional Testing
282(19)
7.3.2 Diagnostic Testing
301(4)
7.3.3 JTAG Interface Model
305(7)
7.3.3.1 BSC Model
307(2)
7.3.3.2 BSC Chain Model
309(2)
7.3.3.3 TAP Controller Model
311(1)
References
312(1)
Index 313


Evgeni Perelroyzen
Lisainfo e-raamatute kohta Lisainfo e-raamatute kohta
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