With vastly increased complexity and functionality in the "nanometer era" (i.e. hundreds of millions of transistors on one chip), increasing the performance of integrated circuits has become a challenging task. This is due primarily to the inevitable increase in the distance among circuit elements and interconnect design solutions have become the greatest determining factor in overall performance.
Three-dimensional (3D) integrated circuits (ICs), which contain multiple layers of active devices, have the potential to enhance dramatically chip performance and functionality, while reducing the distance among devices on a chip. They promise solutions to the current "interconnect bottleneck" challenges faced by IC designers. They also may facilitate the integration of heterogeneous materials, devices, and signals. However, before these advantages can be realized, key technology challenges of 3D ICs must be addressed.
This is the first book on 3-D integrated circuit design, covering all of the technological and design aspects of this emerging design paradigm, while proposing effective solutions to specific challenging problems concerning the design of three-dimensional integrated circuits. A handy, comprehensive reference or a practical design guide, this book provides a sound foundation for the design of three-dimensional integrated circuits.
* Demonstrates how to overcome "Interconnect Bottleneck" with 3D Integrated Circuit Design...leading edge design techniques offer solutions to problems (performance/power consumption/price) faced by all circuit designers.
* The FIRST book on 3D Integrated Circuit Design...provides up-to-date information that is otherwise difficult to find;
* Focuses on design issues key to the product development cyle...good design plays a major role in exploiting the implementation flexibilities offered in the third dimension;
* Provides broad coverage of 3D IC Design, including Interconnect Prediction Models, Thermal Management Techniques, and Timing Optimization...offers practical view of designing 3D circuits.
With vastly increased complexity and functionality in the "nanometer era" (i.e. hundreds of millions of transistors on one chip), increasing the performance of integrated circuits has become a challenging task. Connecting effectively (interconnect design) all of these chip elements has become the greatest determining factor in overall performance. 3-D integrated circuit design may offer the best solutions in the near future.
This is the first book on 3-D integrated circuit design, covering all of the technological and design aspects of this emerging design paradigm, while proposing effective solutions to specific challenging problems concerning the design of 3-D integrated circuits. A handy, comprehensive reference or a practical design guide, this book provides a sound foundation for the design of 3-D integrated circuits.
* Demonstrates how to overcome "interconnect bottleneck" with 3-D integrated circuit design...leading edge design techniques offer solutions to problems (performance/power consumption/price) faced by all circuit designers
* The FIRST book on 3-D integrated circuit design...provides up-to-date information that is otherwise difficult to find
* Focuses on design issues key to the product development cycle...good design plays a major role in exploiting the implementation flexibilities offered in the 3-D
* Provides broad coverage of 3-D integrated circuit design, including interconnect prediction models, thermal management techniques, and timing optimization...offers practical view of designing 3-D circuits
Muu info
Overcome Interconnect Bottleneck at the new frontier of Integrated Circuit Design: 3-Dimensions!
| Preface |
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xiii | |
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1 | (16) |
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From the Integrated Circuit to the Computer |
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2 | (3) |
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Interconnects, an Old Friend |
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5 | (3) |
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Three-Dimensional or Vertical Integration |
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8 | (5) |
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Opportunities for Three-Dimensional Integration |
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9 | (2) |
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Challenges for Three-Dimensional Integration |
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11 | (2) |
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13 | (4) |
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Manufacturing of 3-D Packaged Systems |
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17 | (20) |
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Three-Dimensional Integration |
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17 | (2) |
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18 | (1) |
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Three-Dimensional Integrated Circuits |
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18 | (1) |
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19 | (5) |
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Technologies for System-in-Package |
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24 | (8) |
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Wire-Bonded System-in-Package |
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24 | (2) |
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Peripheral Vertical Interconnects |
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26 | (2) |
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Area Array Vertical Interconnects |
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28 | (2) |
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Metallizing the Walls of an SiP |
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30 | (2) |
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Cost Issues for 3-D Integrated Systems |
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32 | (3) |
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35 | (2) |
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3-D Integrated Circuit Fabrication Technologies |
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37 | (28) |
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38 | (10) |
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38 | (8) |
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46 | (2) |
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3-D ICs with Through Silicon (TSV) or Interplane Vias |
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48 | (5) |
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53 | (3) |
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Capacitively Coupled 3-D ICs |
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53 | (2) |
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Inductively Coupled 3-D ICs |
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55 | (1) |
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Vertical Interconnects for 3-D ICs |
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56 | (7) |
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Electrical Characteristics of Through Silicon Vias |
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61 | (2) |
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63 | (2) |
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Interconnect Prediction Models |
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65 | (14) |
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Interconnect Prediction Models for 2-D Circuits |
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66 | (3) |
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Interconnect Prediction Models for 3-D ICs |
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69 | (4) |
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73 | (4) |
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77 | (2) |
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Physical Design Techniques for 3-D ICs |
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79 | (20) |
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79 | (8) |
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Single-versus Multistep Floorplanning for 3-D ICs |
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81 | (3) |
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Multi-Objective Floorplanning Techniques for 3-D ICs |
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84 | (3) |
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87 | (5) |
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Multi-Objective Placement for 3-D ICs |
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88 | (4) |
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92 | (3) |
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95 | (2) |
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97 | (2) |
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Thermal Management Techniques |
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99 | (36) |
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Thermal Analysis of 3-D ICs |
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100 | (11) |
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Closed-Form Temperature Expressions |
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101 | (7) |
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108 | (2) |
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Mesh-based Thermal Models |
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110 | (1) |
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Thermal Management Techniques without Thermal Vias |
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111 | (9) |
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Thermal-Driven Floorplanning |
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111 | (6) |
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117 | (3) |
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Thermal Management Techniques Employing Thermal Vias |
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120 | (11) |
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Region-Constrained Thermal Via Insertion |
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121 | (3) |
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Thermal Via Planning Techniques |
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124 | (6) |
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130 | (1) |
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131 | (4) |
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Timing Optimization for Two-Terminal Interconnects |
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135 | (34) |
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Interplance Interconnect Models |
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136 | (5) |
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Two-Terminal Nets with a Single-Interplane Via |
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141 | (10) |
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Elmore Delay Model of an Interplane Interconnect |
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141 | (2) |
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Interplane Interconnect Delay |
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143 | (2) |
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145 | (3) |
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Improvement in Interconnect Delay |
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148 | (3) |
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Two-Terminal Interconnects with Multiple-Interplane Vias |
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151 | (16) |
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Two-Terminal Via Placement Heuristic |
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155 | (4) |
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Two-Terminal Via Placement Algorithm |
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159 | (1) |
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Application of the Via Placement Technique |
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160 | (7) |
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167 | (2) |
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Timing Optimization for Multiterminal Interconnects |
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169 | (16) |
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Timing-Driven Via Placement for Interplane Interconnect Trees |
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169 | (4) |
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Multiterminal Interconnect Via Placement Heuristics |
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173 | (3) |
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173 | (1) |
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Single Critical Sink Interconnect Trees |
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174 | (2) |
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Via Placement Algorithms for Interconnect Trees |
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176 | (1) |
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Interconnect Tree Via Placement Algorithm (ITVPA) |
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176 | (1) |
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Single Critical Sink Interconnect Tree via Placement Algorithm (SCSVPA) |
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177 | (1) |
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Via Placement Results and Discussion |
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177 | (6) |
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183 | (2) |
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3-D Circuit Architectures |
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185 | (62) |
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Classification of Wire-Limited 3-D Circuits |
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186 | (1) |
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Three-Dimensional Microprocessors and Memories |
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187 | (10) |
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Three-Dimensional Microprocessor Logic Blocks |
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189 | (1) |
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Three-Dimensional Design of Cache Memories |
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190 | (5) |
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Architecting a 3-D Microprocessor---Memory System |
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195 | (2) |
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Three-Dimensional Networks-on-Chip |
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197 | (34) |
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198 | (2) |
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Zero-Load latency for 3-D NoC |
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200 | (4) |
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Power Consumptionn in 3-D NoC |
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204 | (2) |
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Performance and Power Analysis for 3-D NoC |
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206 | (15) |
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221 | (10) |
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231 | (13) |
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Design Aids for 3-D FPGAs |
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238 | (6) |
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244 | (3) |
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Case Study: Clock Distribution Networks for 3-D ICs |
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247 | (28) |
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MIT Lincoln Laboratories 3-D IC Fabrication Technology |
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248 | (5) |
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253 | (4) |
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Clock Signal Distribution in 3-D Circuits |
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257 | (8) |
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Timing Characteristics of Synchronous Circuits |
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258 | (3) |
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Clock Disbtribution Network Structures within the Test Circuit |
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261 | (4) |
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265 | (7) |
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272 | (3) |
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275 | (4) |
| Appendix A Enumeration of Gate Pairs in a 3-D IC |
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279 | (2) |
| Appendix B Formal Proof of Optimum Single Via Placement |
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281 | (2) |
| Appendix C Proof of the Two-terminal Via Placement Heuristic |
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283 | (4) |
| Appendix D Proof of Condition for Via Placement of Multiterminal Nets |
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287 | (2) |
| References |
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289 | (16) |
| Index |
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305 | |
Vasilis F. Pavlidis received the B.Sc. and M.Eng. degrees in Electrical and Computer Engineering from the Democritus University of Thrace, Greece, in 2000 and 2002, respectively. He received the M.Sc. and Ph.D. degrees in Electrical and Computer Engineering from the University of Rochester, Rochester, NY, in 2003 and 2008, respectively.He is currently an Assistant Professor in the School of Computer Science at the University of Manchester, Manchester, UK. From 2008 to 2012, he was a post-doctoral fellow with the Integrated Systems Laboratory at the Ecole Polytechnique Fédérale de Lausanne, Lausanne, Switzerland. He was with INTRACOM S.A., Athens, Greece, from 2000 to 2002. He has also been a visiting researcher at Synopsys Inc., Mountain View, CA, with the Primetime group in 2007. His current research interests include interconnect modeling and analysis, 3-D and 2.5-D integration, and other issues related to VLSI design. He has published several conference and journal papers in these areas. He was the leading designer of the Rochester cube and co-creator of the Manchester Thermal Analyzer.Dr. Pavlidis is on the editorial board of the Microelectronics Journal and Integration, the VLSI Journal. He also serves on the Technical Program Committees of several IEEE conferences. He is a member of the VLSI Systems & Applications Technical Committee of the Circuits and Systems Society and a member of the IEEE. He is also involved in public policy issues as a member of the ICT working group of the IEEE European Public Policy Initiative. Eby G. Friedman received the B.S. degree from Lafayette College in 1979, and the M.S. and Ph.D. degrees from the University of California, Irvine, in 1981 and 1989, respectively, all in electrical engineering.
From 1979 to 1991, he was with Hughes Aircraft Company, rising to the position of manager of the Signal Processing Design and Test Department, responsible for the design and test of high performance digital and analog integrated circuits. He has been with the Department of Electrical and Computer Engineering at the University of Rochester since 1991, where he is a Distinguished Professor, and the Director of the High Performance VLSI/IC Design and Analysis Laboratory. He is also a Visiting Professor at the Technion - Israel Institute of Technology. His current research and teaching interests are in high performance synchronous digital and mixed-signal microelectronic design and analysis with application to high speed portable processors, low power wireless communications, and power efficient server farms.
He is the author of more than 500 papers and book chapters, 13 patents, and the author or editor of 18 books in the fields of high speed and low power CMOS design techniques, 3-D integration, high speed interconnect, and the theory and application of synchronous clock and power delivery and management. Dr. Friedman is the Editor-in-Chief of the Microelectronics Journal, a Member of the editorial board of the Journal of Low Power Electronics and Journal of Low Power Electronics and Applications, and a Member of the technical program committee of numerous conferences. He previously was the Editor-in-Chief and Chair of the Steering Committee of the IEEE Transactions on Very Large Scale Integration (VLSI) Systems, the Regional Editor of the Journal of Circuits, Systems and Computers, a Member of the editorial board of the Proceedings of the IEEE, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Analog Integrated Circuits and Signal Processing, and Journal of Signal Processing Systems, a Member of the Circuits and Systems (CAS) Society Board of Governors, Program and Technical chair of several IEEE conferences, and a recipient of the IEEE Circuits and Systems 2013 Charles A. Desoer Technical Achievement Award, a University of Rochester Graduate Teaching Award, and a College of Engineering Teaching Excellence Award. Dr. Friedman is an inaugural member of the University of California, Irvine Engineering Hall of Fame, a Senior Fulbright Fellow, and an IEEE Fellow.
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