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xv | |
About the Authors |
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xli | |
Preface to the Second Edition |
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xliii | |
Preface to the First Edition |
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xlv | |
Acknowledgments |
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xlvii | |
Organization of the Book |
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xlix | |
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1 | (14) |
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1.1 Interconnect Issues in Integrated Systems |
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4 | (2) |
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1.2 Three-Dimensional or Vertical Integration |
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6 | (5) |
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1.2.1 Opportunities for Three-Dimensional Integration |
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7 | (2) |
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1.2.2 Challenges of Three-Dimensional Integration |
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9 | (2) |
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11 | (4) |
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Chapter 2 Manufacturing of Three-Dimensional Packaged Systems |
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15 | (22) |
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2.1 Stacking Methods for Transistors, Circuits, and Dies |
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16 | (2) |
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17 | (1) |
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2.1.2 Transistor and Circuit Level Stacking |
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17 | (1) |
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18 | (3) |
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2.3 Technologies for System-in-Package |
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21 | (8) |
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2.3.1 Wire Bonded System-in-Package |
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22 | (1) |
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2.3.2 Peripheral Vertical Interconnects |
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23 | (3) |
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2.3.3 Area Array Vertical Interconnects |
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26 | (1) |
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2.3.4 Metalizing the Walls of an SiP |
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27 | (2) |
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2.4 Technologies for 2.5-D Integration |
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29 | (6) |
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2.4.1 Interposer Materials |
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30 | (1) |
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2.4.2 Metallization Processes |
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31 | (1) |
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2.4.3 Vertical Interconnects |
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32 | (3) |
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35 | (2) |
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Chapter 3 Manufacturing Technologies for Three-Dimensional Integrated Circuits |
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37 | (30) |
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3.1 Monolithic Three-Dimensional ICs |
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38 | (10) |
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3.1.1 Laser Crystallization |
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39 | (2) |
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3.1.2 Seed Crystallization |
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41 | (1) |
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3.1.3 Double-Gate Metal Oxide Semiconductor Field Effect Transistors for Stacked Three-Dimensional ICs |
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42 | (3) |
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45 | (3) |
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3.2 Three-Dimensional ICs with Through Silicon Via or Intertier Via |
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48 | (7) |
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3.2.1 Wafer Level Integration |
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48 | (3) |
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3.2.2 Die-to-Die Integration |
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51 | (2) |
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3.2.3 Bonding of Three-Dimensional ICs |
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53 | (2) |
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3.3 Contactless Three-Dimensional ICs |
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55 | (3) |
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3.3.1 Capacitively Coupled Three-Dimensional ICs |
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56 | (1) |
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3.3.2 Inductively Coupled Three-Dimensional ICs |
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57 | (1) |
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3.4 Vertical Interconnects for Three-Dimensional ICs |
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58 | (6) |
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64 | (3) |
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Chapter 4 Electrical Properties of Through Silicon Vias |
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67 | (52) |
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4.1 Physical Characteristics of a Through Silicon Via |
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69 | (1) |
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4.2 Electrical Model of Through Silicon Via |
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70 | (1) |
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4.3 Modeling a Three-Dimensional Via as a Cylinder |
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71 | (2) |
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73 | (9) |
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4.4.1 Physical Parameters of Compact Resistance Models |
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73 | (2) |
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4.4.2 Physical Parameters of Compact Inductance Models |
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75 | (3) |
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4.4.3 Physical Parameters of Compact Capacitance Models |
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78 | (3) |
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4.4.4 Physical Parameters of Compact Conductance Models |
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81 | (1) |
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4.5 Through Silicon Via Impedance Models |
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82 | (23) |
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4.5.1 Compact Resistance Model of a Three-Dimensional Via |
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82 | (3) |
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4.5.2 Compact Inductance Model of a Three-Dimensional Via |
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85 | (9) |
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4.5.3 Compact Capacitance Model of a Three-Dimensional Via |
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94 | (10) |
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4.5.4 Compact Conductance Model of a Three-Dimensional Via |
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104 | (1) |
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4.6 Electrical Characterization Through Numerical Simulation |
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105 | (2) |
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4.6.1 Ansys Quick Three-Dimensional Electromagnetic Field Solver |
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106 | (1) |
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4.6.2 Numerical Analysis of Through Silicon Via Impedance |
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107 | (1) |
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4.7 Case Study---Through Silicon Via Characterization of the MITLL TSV process |
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107 | (9) |
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4.7.1 MIT Lincoln Laboratory Three-Dimensional Process |
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108 | (1) |
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4.7.2 RLC Extraction of a Single Three-Dimensional Via |
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109 | (1) |
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4.7.3 RLC Coupling Between Two Three-Dimensional Vias |
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109 | (2) |
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4.7.4 Effects of Three-Dimensional Via Placement on Shielding |
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111 | (3) |
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4.7.5 Effect of the Return Path on Three-Dimensional Via Inductance |
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114 | (2) |
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116 | (3) |
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Chapter 5 Substrate Noise Coupling in Heterogeneous Three-Dimensional ICs |
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119 | (18) |
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5.1 Heterogeneous Substrate Coupling |
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120 | (4) |
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5.1.1 Common Circuits and Compatible Substrate Types |
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120 | (1) |
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5.1.2 Resistive Properties of Different Substrate Materials |
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121 | (1) |
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5.1.3 Noise Model Reduction for Different Substrate Materials |
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121 | (3) |
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124 | (3) |
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5.2.1 Isolation Efficiency of Noise Coupled System |
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124 | (1) |
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5.2.2 Transfer Function of Noise Coupled System |
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124 | (3) |
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5.3 Techniques to Improve Noise Isolation |
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127 | (8) |
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5.3.1 Ground Network Inductance |
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127 | (1) |
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5.3.2 Distance Between Aggressor and Victim |
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128 | (7) |
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135 | (2) |
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Chapter 6 Three-Dimensional ICs with Inductive Links |
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137 | (26) |
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6.1 Wireless On-Chip Communication Interfaces |
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138 | (2) |
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138 | (2) |
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6.2 On-Chip Inductors for Intertier Links |
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140 | (3) |
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6.2.1 Intertier Coupling Efficiency |
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141 | (1) |
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6.2.2 Geometry and Electrical Characteristics of Inductor |
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142 | (1) |
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6.2.3 Design Flow for Inductive Link Coils |
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143 | (1) |
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6.3 Transmitter and Receiver Circuits |
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143 | (6) |
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6.3.1 Design of Synchronous Inductive Link Transceivers |
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143 | (2) |
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6.3.2 Asynchronous Data Transmission and Recovery |
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145 | (3) |
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6.3.3 Burst Data Transmission |
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148 | (1) |
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6.4 Challenges for Wireless On-Chip Communication |
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149 | (9) |
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6.4.1 Performance and Area Analysis |
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149 | (2) |
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6.4.2 Crosstalk Between Inductive Links |
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151 | (1) |
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6.4.3 Crosstalk Noise on Adjacent On-Chip Components |
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152 | (6) |
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6.5 Intertier Power Transfer |
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158 | (3) |
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161 | (2) |
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Chapter 7 Interconnect Prediction Models |
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163 | (12) |
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7.1 Interconnect Prediction Models for Two-Dimensional Circuits |
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163 | (3) |
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7.2 Interconnect Prediction Models for Three-Dimensional ICs |
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166 | (4) |
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7.3 Projections for Three-Dimensional ICs |
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170 | (3) |
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173 | (2) |
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Chapter 8 Cost Considerations for Three-Dimensional Integration |
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175 | (28) |
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8.1 Through Silicon Via Processing Options |
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176 | (12) |
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8.1.1 TSV Flows and Geometries |
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177 | (1) |
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8.1.2 Cost Comparison of Through Silicon Via Processing Steps |
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178 | (8) |
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8.1.3 Comparison of Through Silicon Via Processing Cost |
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186 | (2) |
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8.2 Interposer-Based Systems Integration |
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188 | (4) |
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8.2.1 Cost of Interposer Manufacturing Features |
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189 | (2) |
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8.2.2 Interposer Build-Up Configurations |
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191 | (1) |
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8.3 Comparison of Processing Cost for 2.5-D and Three-Dimensional Integration |
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192 | (8) |
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8.3.1 Components of a Three-Dimensional Stacked System |
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193 | (1) |
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8.3.2 Cost of Three-Dimensional Integration Components |
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194 | (1) |
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8.3.3 Comparison of Three-Dimensional System Cost |
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195 | (2) |
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8.3.4 Dependence of Three-Dimensional System Cost on Active Die Size |
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197 | (1) |
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8.3.5 Variation of Interposer Process Yield and Prestack Fault Coverage |
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198 | (2) |
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200 | (3) |
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Chapter 9 Physical Design Techniques for Three-Dimensional ICs |
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203 | (50) |
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9.1 Floorplanning Techniques |
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204 | (4) |
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9.1.1 Sequence Pair Technique |
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205 | (3) |
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9.2 Floorplanning Three-Dimensional ICs |
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208 | (18) |
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9.2.1 Floorplanning Three-Dimensional Circuits Without Through Silicon Via Planning |
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209 | (5) |
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9.2.2 Floorplanning Techniques for Three-Dimensional ICs With Through Silicon Via Planning |
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214 | (12) |
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226 | (4) |
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9.3.1 Placement Using the Force Directed Method |
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226 | (4) |
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9.4 Placement in Three-Dimensional ICs |
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230 | (15) |
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9.4.1 Force Directed Placement of Three-Dimensional ICs |
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231 | (3) |
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9.4.2 Other Objectives in Placement Process |
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234 | (2) |
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9.4.3 Analytic Placement for Three-Dimensional ICs |
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236 | (3) |
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9.4.4 Placement for Three-Dimensional ICs Using Simulated Annealing |
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239 | (2) |
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9.4.5 Supercell-Based Placement for Three-Dimensional Circuits |
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241 | (4) |
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245 | (5) |
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250 | (1) |
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251 | (2) |
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Chapter 10 Timing Optimization for Two-Terminal Interconnects |
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253 | (28) |
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10.1 Intertier Interconnect Models |
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254 | (2) |
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10.2 Two-Terminal Nets With a Single Intertier Via |
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256 | (10) |
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10.2.1 Elmore Delay Model of an Intertier Interconnect |
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257 | (3) |
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10.2.2 Intertier Interconnect Delay |
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260 | (1) |
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10.2.3 Optimum Via Location |
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261 | (3) |
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10.2.4 Improvement in Interconnect Delay |
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264 | (2) |
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10.3 Two Terminal Interconnects With Multiple Intertier Vias |
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266 | (13) |
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10.3.1 Two Terminal Via Placement Heuristic |
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269 | (3) |
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10.3.2 Two Terminal Via Placement Algorithm |
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272 | (1) |
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10.3.3 Application of the Via Placement Technique |
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273 | (6) |
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279 | (2) |
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Chapter 11 Timing Optimization for Multiterminal Interconnects |
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281 | (14) |
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11.1 Timing Driven Via Placement for Intertier Interconnect Trees |
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282 | (2) |
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11.2 Multiterminal Interconnect Via Placement Heuristics |
|
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284 | (3) |
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11.2.1 Interconnect Trees |
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285 | (1) |
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11.2.2 Single Critical Sink Interconnect Trees |
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286 | (1) |
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11.3 Via Placement Algorithms for Interconnect Trees |
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287 | (1) |
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11.3.1 Interconnect Tree Via Placement Algorithm (ITVPA) |
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287 | (1) |
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11.3.2 Single Critical Sink Interconnect Tree Via Placement Algorithm |
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288 | (1) |
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11.4 Discussion of Via Placement Results |
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288 | (4) |
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292 | (3) |
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Chapter 12 Thermal Modeling and Analysis |
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295 | (38) |
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12.1 Heat Transfer in Three-Dimensional ICs |
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296 | (7) |
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298 | (5) |
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12.2 Closed-Form Temperature Models |
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303 | (7) |
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12.3 Mesh-Based Thermal Models |
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310 | (14) |
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12.3.1 Thermal Model of Through Silicon Vias |
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313 | (8) |
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12.3.2 Thermal Models of Microchannels for Liquid Cooling |
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321 | (3) |
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12.4 Thermal Analysis Techniques |
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324 | (6) |
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330 | (3) |
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Chapter 13 Thermal Management Strategies for Three-Dimensional ICs |
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333 | (48) |
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13.1 Thermal Management Through Power Density Reduction |
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334 | (24) |
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13.1.1 Thermal Driven Floorplanning |
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334 | (10) |
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13.1.2 Thermal Driven Placement |
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344 | (1) |
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13.1.3 Dynamic Thermal Management Techniques |
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345 | (13) |
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13.2 Thermal Management Through Enhanced Thermal Conductivity |
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358 | (17) |
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13.2.1 Thermal Via Planning Under Temperature Objectives |
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360 | (7) |
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13.2.2 Thermal Via Planning Under Temperature Constraints |
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367 | (1) |
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13.2.3 Multi-Level Routing |
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368 | (4) |
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13.2.4 Thermal Wire Insertion |
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372 | (3) |
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13.3 Hybrid Methodologies for Thermal Management |
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375 | (3) |
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378 | (3) |
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Chapter 14 Case Study: Thermal Coupling in 3-D Integrated Circuits |
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381 | (28) |
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14.1 Thermal Propagation Test Circuit |
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|
382 | (2) |
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14.1.1 3-D IC Fabrication Technology |
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383 | (1) |
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|
383 | (1) |
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14.2 Setup and Experiments |
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|
384 | (11) |
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14.3 Design Considerations Based on Experimental Results |
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|
395 | (6) |
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14.3.1 Effect of Block Placement on Hot Spot Formation and Mitigation Techniques |
|
|
395 | (1) |
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14.3.2 Horizontal and Vertical Thermal Conduits |
|
|
395 | (4) |
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14.3.3 Multiple Aligned Active Blocks |
|
|
399 | (1) |
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14.3.4 Multiple Nonaligned Active Blocks |
|
|
399 | (2) |
|
14.3.5 Additional Design Considerations |
|
|
401 | (1) |
|
14.4 Verification of Experimental Results with Simulations |
|
|
401 | (7) |
|
14.4.1 Simulation Setup and Tools |
|
|
403 | (1) |
|
14.4.2 Comparison to Experimental Results |
|
|
403 | (4) |
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14.4.3 Effect of Density of TSVs on Thermal Coupling |
|
|
407 | (1) |
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|
408 | (1) |
|
Chapter 15 Synchronization in Three-Dimensional ICs |
|
|
409 | (40) |
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15.1 Synthesis Techniques for Planar Clock Distribution Networks |
|
|
410 | (7) |
|
15.1.1 Method of Means and Medians |
|
|
411 | (2) |
|
15.1.2 Deferred-Merge Embedding Method |
|
|
413 | (4) |
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15.2 Global Three-Dimensional Clock Distribution Networks |
|
|
417 | (6) |
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15.3 Synthesis of Three-Dimensional Clock Distribution Networks |
|
|
423 | (17) |
|
15.3.1 Standard Synthesis Techniques |
|
|
424 | (7) |
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15.3.2 Synthesis Techniques for Pre-bond Testable Three-Dimensional Clock Trees |
|
|
431 | (9) |
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15.4 Practical Considerations of Three-Dimensional Clock Tree Synthesis |
|
|
440 | (6) |
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|
446 | (3) |
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Chapter 16 Case Study: Clock Distribution Networks for Three-Dimensional ICs |
|
|
449 | (26) |
|
16.1 MIT Lincoln Laboratories Three-Dimensional IC Fabrication Technology |
|
|
449 | (5) |
|
16.2 Three-Dimensional Test Circuit Architecture |
|
|
454 | (4) |
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16.3 Clock Distribution Network Structures Within the Test Circuit |
|
|
458 | (5) |
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16.4 Models of the Clock Distribution Network Topologies Incorporating Three-Dimensional Via Impedance |
|
|
463 | (4) |
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16.5 Experimental Results |
|
|
467 | (6) |
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|
473 | (2) |
|
Chapter 17 Variability Issues in Three-Dimensional ICs |
|
|
475 | (44) |
|
17.1 Process Variations in Data Paths Within Three-Dimensional ICs |
|
|
477 | (5) |
|
17.2 Effects of Process Variations on Clock Paths |
|
|
482 | (13) |
|
17.2.1 Statistical Delay Model of Clock Buffers |
|
|
483 | (1) |
|
17.2.2 Delay Distribution of Clock Paths |
|
|
484 | (3) |
|
17.2.3 Clock Skew Distribution in Three-Dimensional Clock Trees |
|
|
487 | (4) |
|
17.2.4 Skew Variations in Three-Dimensional Clock Tree Topologies |
|
|
491 | (4) |
|
17.3 Effect of Process and Power Supply Variations on Three-Dimensional Clock Distribution Networks |
|
|
495 | (22) |
|
17.3.1 Delay Variation of Buffer Stages |
|
|
496 | (4) |
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17.3.2 Model of Skitter in Three-Dimensional Clock Trees |
|
|
500 | (3) |
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17.3.3 Skitter Related Tradeoffs in Three-Dimensional ICs |
|
|
503 | (9) |
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17.3.4 Effect of Skitter on Synthesized Clock Trees |
|
|
512 | (5) |
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|
517 | (2) |
|
Chapter 18 Power Delivery for Three-Dimensional ICs |
|
|
519 | (46) |
|
18.1 The Power Delivery Challenge |
|
|
521 | (9) |
|
18.1.1 Multilevel Power Delivery for Three-Dimensional ICs |
|
|
526 | (4) |
|
18.2 Models for Three-Dimensional Power Distribution Networks |
|
|
530 | (10) |
|
18.2.1 Electro-Thermal Model of Power Distribution Networks |
|
|
537 | (3) |
|
18.3 Through Silicon Via Technologies to Mitigate Power Supply Noise |
|
|
540 | (11) |
|
18.3.1 Enhanced Power Integrity by Exploiting Through Silicon Via Paths |
|
|
545 | (4) |
|
18.3.2 Effect of Through Silicon Via Tapering on Power Distribution Networks |
|
|
549 | (2) |
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18.4 Decoupling Capacitance for Three-Dimensional Power Distribution Networks |
|
|
551 | (6) |
|
18.4.1 Decoupling Capacitance Topologies for Power Gated Three-Dimensional ICs |
|
|
553 | (4) |
|
18.5 Wire Sizing Methods in Three-Dimensional Power Distribution Networks |
|
|
557 | (5) |
|
|
562 | (3) |
|
Chapter 19 Case Study: 3-D Power Distribution Topologies and Models |
|
|
565 | (40) |
|
19.1 3-D Power Distribution Network Test Circuit |
|
|
566 | (18) |
|
19.1.1 3-D Power Topologies |
|
|
566 | (1) |
|
19.1.2 Layouts and Schematics of the 3-D Test Circuit |
|
|
567 | (11) |
|
19.1.3 3-D Circuit Architecture |
|
|
578 | (4) |
|
19.1.4 3-D IC Fabrication Technology |
|
|
582 | (2) |
|
19.2 Experimental Results |
|
|
584 | (6) |
|
19.3 Characteristics of 3-D Power Distribution Topologies |
|
|
590 | (13) |
|
19.3.1 Pre-Layout Design Considerations |
|
|
590 | (12) |
|
19.3.2 Design Considerations Based on Experimental Results |
|
|
602 | (1) |
|
|
603 | (2) |
|
Chapter 20 3-D Circuit Architectures |
|
|
605 | (44) |
|
20.1 Classification of Wire Limited 3-D Circuits |
|
|
606 | (1) |
|
20.2 3-D Microprocessors and Memories |
|
|
607 | (8) |
|
20.2.1 3-D Microprocessor Logic Blocks |
|
|
608 | (2) |
|
20.2.2 3-D Design of Cache Memories |
|
|
610 | (3) |
|
20.2.3 Architecting a 3-D Microprocessor Memory System |
|
|
613 | (2) |
|
20.3 3-D Networks-on-Chip |
|
|
615 | (24) |
|
20.3.1 3-D NoC Topologies |
|
|
616 | (1) |
|
20.3.2 Zero-Load Latency for 3-D NoC |
|
|
617 | (4) |
|
20.3.3 Power Consumption in 3-D NoC |
|
|
621 | (2) |
|
20.3.4 Performance and Power Analysis for 3-D NoC |
|
|
623 | (16) |
|
|
639 | (7) |
|
|
646 | (3) |
|
|
649 | (4) |
Appendix A Enumeration of Gate Pairs in a 3-D IC |
|
653 | (2) |
Appendix B Formal Proof of Optimum Single Via Placement |
|
655 | (2) |
Appendix C Proof of the Two-Terminal Via Placement Heuristic |
|
657 | (2) |
Appendix D Proof of Condition for Via Placement of Multi-terminal Nets |
|
659 | (2) |
Appendix E Correlation of WID Variations for Intratier Buffers |
|
661 | (2) |
Appendix F Extension of the Proposed Model to Include Variations of Wires |
|
663 | (2) |
Glossary of Terms |
|
665 | (4) |
References |
|
669 | (40) |
Index |
|
709 | |