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E-raamat: Three-Dimensional Integrated Circuit Design

(Assistant Professor, Department of Electrical and Computer Engineering, Drexel University, Philadelphia, USA), (Distinguished Professor, Department of El), (Assistant Professor, School of Computer Science, University of Manchester, UK)
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  • ISBN-13: 9780124104846
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  • Formaat: PDF+DRM
  • Ilmumisaeg: 04-Jul-2017
  • Kirjastus: Morgan Kaufmann Publishers In
  • Keel: eng
  • ISBN-13: 9780124104846

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Three-Dimensional Integrated Circuit Design, Second Eition, expands the original with more than twice as much new content, adding the latest developments in circuit models, temperature considerations, power management, memory issues, and heterogeneous integration. 3-D IC experts Pavlidis, Savidis, and Friedman cover the full product development cycle throughout the book, emphasizing not only physical design, but also algorithms and system-level considerations to increase speed while conserving energy. A handy, comprehensive reference or a practical design guide, this book provides effective solutions to specific challenging problems concerning the design of three-dimensional integrated circuits.

Expanded with new chapters and updates throughout based on the latest research in 3-D integration:





Manufacturing techniques for 3-D ICs with TSVs Electrical modeling and closed-form expressions of through silicon vias Substrate noise coupling in heterogeneous 3-D ICs Design of 3-D ICs with inductive links Synchronization in 3-D ICs Variation effects on 3-D ICs Correlation of WID variations for intra-tier buffers and wires

Muu info

This updated reference explores the latest developments in 3D integrated circuit design, including how to increase speed while conserving energy
List of Figures
xv
About the Authors xli
Preface to the Second Edition xliii
Preface to the First Edition xlv
Acknowledgments xlvii
Organization of the Book xlix
Chapter 1 Introduction
1(14)
1.1 Interconnect Issues in Integrated Systems
4(2)
1.2 Three-Dimensional or Vertical Integration
6(5)
1.2.1 Opportunities for Three-Dimensional Integration
7(2)
1.2.2 Challenges of Three-Dimensional Integration
9(2)
1.3 Book Organization
11(4)
Chapter 2 Manufacturing of Three-Dimensional Packaged Systems
15(22)
2.1 Stacking Methods for Transistors, Circuits, and Dies
16(2)
2.1.1 System-in-Package
17(1)
2.1.2 Transistor and Circuit Level Stacking
17(1)
2.2 System-on-Package
18(3)
2.3 Technologies for System-in-Package
21(8)
2.3.1 Wire Bonded System-in-Package
22(1)
2.3.2 Peripheral Vertical Interconnects
23(3)
2.3.3 Area Array Vertical Interconnects
26(1)
2.3.4 Metalizing the Walls of an SiP
27(2)
2.4 Technologies for 2.5-D Integration
29(6)
2.4.1 Interposer Materials
30(1)
2.4.2 Metallization Processes
31(1)
2.4.3 Vertical Interconnects
32(3)
2.5 Summary
35(2)
Chapter 3 Manufacturing Technologies for Three-Dimensional Integrated Circuits
37(30)
3.1 Monolithic Three-Dimensional ICs
38(10)
3.1.1 Laser Crystallization
39(2)
3.1.2 Seed Crystallization
41(1)
3.1.3 Double-Gate Metal Oxide Semiconductor Field Effect Transistors for Stacked Three-Dimensional ICs
42(3)
3.1.4 Molecular Bonding
45(3)
3.2 Three-Dimensional ICs with Through Silicon Via or Intertier Via
48(7)
3.2.1 Wafer Level Integration
48(3)
3.2.2 Die-to-Die Integration
51(2)
3.2.3 Bonding of Three-Dimensional ICs
53(2)
3.3 Contactless Three-Dimensional ICs
55(3)
3.3.1 Capacitively Coupled Three-Dimensional ICs
56(1)
3.3.2 Inductively Coupled Three-Dimensional ICs
57(1)
3.4 Vertical Interconnects for Three-Dimensional ICs
58(6)
3.5 Summary
64(3)
Chapter 4 Electrical Properties of Through Silicon Vias
67(52)
4.1 Physical Characteristics of a Through Silicon Via
69(1)
4.2 Electrical Model of Through Silicon Via
70(1)
4.3 Modeling a Three-Dimensional Via as a Cylinder
71(2)
4.4 Compact Models
73(9)
4.4.1 Physical Parameters of Compact Resistance Models
73(2)
4.4.2 Physical Parameters of Compact Inductance Models
75(3)
4.4.3 Physical Parameters of Compact Capacitance Models
78(3)
4.4.4 Physical Parameters of Compact Conductance Models
81(1)
4.5 Through Silicon Via Impedance Models
82(23)
4.5.1 Compact Resistance Model of a Three-Dimensional Via
82(3)
4.5.2 Compact Inductance Model of a Three-Dimensional Via
85(9)
4.5.3 Compact Capacitance Model of a Three-Dimensional Via
94(10)
4.5.4 Compact Conductance Model of a Three-Dimensional Via
104(1)
4.6 Electrical Characterization Through Numerical Simulation
105(2)
4.6.1 Ansys Quick Three-Dimensional Electromagnetic Field Solver
106(1)
4.6.2 Numerical Analysis of Through Silicon Via Impedance
107(1)
4.7 Case Study---Through Silicon Via Characterization of the MITLL TSV process
107(9)
4.7.1 MIT Lincoln Laboratory Three-Dimensional Process
108(1)
4.7.2 RLC Extraction of a Single Three-Dimensional Via
109(1)
4.7.3 RLC Coupling Between Two Three-Dimensional Vias
109(2)
4.7.4 Effects of Three-Dimensional Via Placement on Shielding
111(3)
4.7.5 Effect of the Return Path on Three-Dimensional Via Inductance
114(2)
4.8 Summary
116(3)
Chapter 5 Substrate Noise Coupling in Heterogeneous Three-Dimensional ICs
119(18)
5.1 Heterogeneous Substrate Coupling
120(4)
5.1.1 Common Circuits and Compatible Substrate Types
120(1)
5.1.2 Resistive Properties of Different Substrate Materials
121(1)
5.1.3 Noise Model Reduction for Different Substrate Materials
121(3)
5.2 Frequency Response
124(3)
5.2.1 Isolation Efficiency of Noise Coupled System
124(1)
5.2.2 Transfer Function of Noise Coupled System
124(3)
5.3 Techniques to Improve Noise Isolation
127(8)
5.3.1 Ground Network Inductance
127(1)
5.3.2 Distance Between Aggressor and Victim
128(7)
5.4 Summary
135(2)
Chapter 6 Three-Dimensional ICs with Inductive Links
137(26)
6.1 Wireless On-Chip Communication Interfaces
138(2)
6.1.1 Inductive Links
138(2)
6.2 On-Chip Inductors for Intertier Links
140(3)
6.2.1 Intertier Coupling Efficiency
141(1)
6.2.2 Geometry and Electrical Characteristics of Inductor
142(1)
6.2.3 Design Flow for Inductive Link Coils
143(1)
6.3 Transmitter and Receiver Circuits
143(6)
6.3.1 Design of Synchronous Inductive Link Transceivers
143(2)
6.3.2 Asynchronous Data Transmission and Recovery
145(3)
6.3.3 Burst Data Transmission
148(1)
6.4 Challenges for Wireless On-Chip Communication
149(9)
6.4.1 Performance and Area Analysis
149(2)
6.4.2 Crosstalk Between Inductive Links
151(1)
6.4.3 Crosstalk Noise on Adjacent On-Chip Components
152(6)
6.5 Intertier Power Transfer
158(3)
6.6 Summary
161(2)
Chapter 7 Interconnect Prediction Models
163(12)
7.1 Interconnect Prediction Models for Two-Dimensional Circuits
163(3)
7.2 Interconnect Prediction Models for Three-Dimensional ICs
166(4)
7.3 Projections for Three-Dimensional ICs
170(3)
7.4 Summary
173(2)
Chapter 8 Cost Considerations for Three-Dimensional Integration
175(28)
8.1 Through Silicon Via Processing Options
176(12)
8.1.1 TSV Flows and Geometries
177(1)
8.1.2 Cost Comparison of Through Silicon Via Processing Steps
178(8)
8.1.3 Comparison of Through Silicon Via Processing Cost
186(2)
8.2 Interposer-Based Systems Integration
188(4)
8.2.1 Cost of Interposer Manufacturing Features
189(2)
8.2.2 Interposer Build-Up Configurations
191(1)
8.3 Comparison of Processing Cost for 2.5-D and Three-Dimensional Integration
192(8)
8.3.1 Components of a Three-Dimensional Stacked System
193(1)
8.3.2 Cost of Three-Dimensional Integration Components
194(1)
8.3.3 Comparison of Three-Dimensional System Cost
195(2)
8.3.4 Dependence of Three-Dimensional System Cost on Active Die Size
197(1)
8.3.5 Variation of Interposer Process Yield and Prestack Fault Coverage
198(2)
8.4 Summary
200(3)
Chapter 9 Physical Design Techniques for Three-Dimensional ICs
203(50)
9.1 Floorplanning Techniques
204(4)
9.1.1 Sequence Pair Technique
205(3)
9.2 Floorplanning Three-Dimensional ICs
208(18)
9.2.1 Floorplanning Three-Dimensional Circuits Without Through Silicon Via Planning
209(5)
9.2.2 Floorplanning Techniques for Three-Dimensional ICs With Through Silicon Via Planning
214(12)
9.3 Placement Techniques
226(4)
9.3.1 Placement Using the Force Directed Method
226(4)
9.4 Placement in Three-Dimensional ICs
230(15)
9.4.1 Force Directed Placement of Three-Dimensional ICs
231(3)
9.4.2 Other Objectives in Placement Process
234(2)
9.4.3 Analytic Placement for Three-Dimensional ICs
236(3)
9.4.4 Placement for Three-Dimensional ICs Using Simulated Annealing
239(2)
9.4.5 Supercell-Based Placement for Three-Dimensional Circuits
241(4)
9.5 Routing Techniques
245(5)
9.6 Layout Tools
250(1)
9.7 Summary
251(2)
Chapter 10 Timing Optimization for Two-Terminal Interconnects
253(28)
10.1 Intertier Interconnect Models
254(2)
10.2 Two-Terminal Nets With a Single Intertier Via
256(10)
10.2.1 Elmore Delay Model of an Intertier Interconnect
257(3)
10.2.2 Intertier Interconnect Delay
260(1)
10.2.3 Optimum Via Location
261(3)
10.2.4 Improvement in Interconnect Delay
264(2)
10.3 Two Terminal Interconnects With Multiple Intertier Vias
266(13)
10.3.1 Two Terminal Via Placement Heuristic
269(3)
10.3.2 Two Terminal Via Placement Algorithm
272(1)
10.3.3 Application of the Via Placement Technique
273(6)
10.4 Summary
279(2)
Chapter 11 Timing Optimization for Multiterminal Interconnects
281(14)
11.1 Timing Driven Via Placement for Intertier Interconnect Trees
282(2)
11.2 Multiterminal Interconnect Via Placement Heuristics
284(3)
11.2.1 Interconnect Trees
285(1)
11.2.2 Single Critical Sink Interconnect Trees
286(1)
11.3 Via Placement Algorithms for Interconnect Trees
287(1)
11.3.1 Interconnect Tree Via Placement Algorithm (ITVPA)
287(1)
11.3.2 Single Critical Sink Interconnect Tree Via Placement Algorithm
288(1)
11.4 Discussion of Via Placement Results
288(4)
11.5 Summary
292(3)
Chapter 12 Thermal Modeling and Analysis
295(38)
12.1 Heat Transfer in Three-Dimensional ICs
296(7)
12.1.1 Liquid Cooling
298(5)
12.2 Closed-Form Temperature Models
303(7)
12.3 Mesh-Based Thermal Models
310(14)
12.3.1 Thermal Model of Through Silicon Vias
313(8)
12.3.2 Thermal Models of Microchannels for Liquid Cooling
321(3)
12.4 Thermal Analysis Techniques
324(6)
12.5 Summary
330(3)
Chapter 13 Thermal Management Strategies for Three-Dimensional ICs
333(48)
13.1 Thermal Management Through Power Density Reduction
334(24)
13.1.1 Thermal Driven Floorplanning
334(10)
13.1.2 Thermal Driven Placement
344(1)
13.1.3 Dynamic Thermal Management Techniques
345(13)
13.2 Thermal Management Through Enhanced Thermal Conductivity
358(17)
13.2.1 Thermal Via Planning Under Temperature Objectives
360(7)
13.2.2 Thermal Via Planning Under Temperature Constraints
367(1)
13.2.3 Multi-Level Routing
368(4)
13.2.4 Thermal Wire Insertion
372(3)
13.3 Hybrid Methodologies for Thermal Management
375(3)
13.4 Summary
378(3)
Chapter 14 Case Study: Thermal Coupling in 3-D Integrated Circuits
381(28)
14.1 Thermal Propagation Test Circuit
382(2)
14.1.1 3-D IC Fabrication Technology
383(1)
14.1.2 3-D Test Circuit
383(1)
14.2 Setup and Experiments
384(11)
14.3 Design Considerations Based on Experimental Results
395(6)
14.3.1 Effect of Block Placement on Hot Spot Formation and Mitigation Techniques
395(1)
14.3.2 Horizontal and Vertical Thermal Conduits
395(4)
14.3.3 Multiple Aligned Active Blocks
399(1)
14.3.4 Multiple Nonaligned Active Blocks
399(2)
14.3.5 Additional Design Considerations
401(1)
14.4 Verification of Experimental Results with Simulations
401(7)
14.4.1 Simulation Setup and Tools
403(1)
14.4.2 Comparison to Experimental Results
403(4)
14.4.3 Effect of Density of TSVs on Thermal Coupling
407(1)
14.5 Summary
408(1)
Chapter 15 Synchronization in Three-Dimensional ICs
409(40)
15.1 Synthesis Techniques for Planar Clock Distribution Networks
410(7)
15.1.1 Method of Means and Medians
411(2)
15.1.2 Deferred-Merge Embedding Method
413(4)
15.2 Global Three-Dimensional Clock Distribution Networks
417(6)
15.3 Synthesis of Three-Dimensional Clock Distribution Networks
423(17)
15.3.1 Standard Synthesis Techniques
424(7)
15.3.2 Synthesis Techniques for Pre-bond Testable Three-Dimensional Clock Trees
431(9)
15.4 Practical Considerations of Three-Dimensional Clock Tree Synthesis
440(6)
15.5 Summary
446(3)
Chapter 16 Case Study: Clock Distribution Networks for Three-Dimensional ICs
449(26)
16.1 MIT Lincoln Laboratories Three-Dimensional IC Fabrication Technology
449(5)
16.2 Three-Dimensional Test Circuit Architecture
454(4)
16.3 Clock Distribution Network Structures Within the Test Circuit
458(5)
16.4 Models of the Clock Distribution Network Topologies Incorporating Three-Dimensional Via Impedance
463(4)
16.5 Experimental Results
467(6)
16.6 Summary
473(2)
Chapter 17 Variability Issues in Three-Dimensional ICs
475(44)
17.1 Process Variations in Data Paths Within Three-Dimensional ICs
477(5)
17.2 Effects of Process Variations on Clock Paths
482(13)
17.2.1 Statistical Delay Model of Clock Buffers
483(1)
17.2.2 Delay Distribution of Clock Paths
484(3)
17.2.3 Clock Skew Distribution in Three-Dimensional Clock Trees
487(4)
17.2.4 Skew Variations in Three-Dimensional Clock Tree Topologies
491(4)
17.3 Effect of Process and Power Supply Variations on Three-Dimensional Clock Distribution Networks
495(22)
17.3.1 Delay Variation of Buffer Stages
496(4)
17.3.2 Model of Skitter in Three-Dimensional Clock Trees
500(3)
17.3.3 Skitter Related Tradeoffs in Three-Dimensional ICs
503(9)
17.3.4 Effect of Skitter on Synthesized Clock Trees
512(5)
17.4 Summary
517(2)
Chapter 18 Power Delivery for Three-Dimensional ICs
519(46)
18.1 The Power Delivery Challenge
521(9)
18.1.1 Multilevel Power Delivery for Three-Dimensional ICs
526(4)
18.2 Models for Three-Dimensional Power Distribution Networks
530(10)
18.2.1 Electro-Thermal Model of Power Distribution Networks
537(3)
18.3 Through Silicon Via Technologies to Mitigate Power Supply Noise
540(11)
18.3.1 Enhanced Power Integrity by Exploiting Through Silicon Via Paths
545(4)
18.3.2 Effect of Through Silicon Via Tapering on Power Distribution Networks
549(2)
18.4 Decoupling Capacitance for Three-Dimensional Power Distribution Networks
551(6)
18.4.1 Decoupling Capacitance Topologies for Power Gated Three-Dimensional ICs
553(4)
18.5 Wire Sizing Methods in Three-Dimensional Power Distribution Networks
557(5)
18.6 Summary
562(3)
Chapter 19 Case Study: 3-D Power Distribution Topologies and Models
565(40)
19.1 3-D Power Distribution Network Test Circuit
566(18)
19.1.1 3-D Power Topologies
566(1)
19.1.2 Layouts and Schematics of the 3-D Test Circuit
567(11)
19.1.3 3-D Circuit Architecture
578(4)
19.1.4 3-D IC Fabrication Technology
582(2)
19.2 Experimental Results
584(6)
19.3 Characteristics of 3-D Power Distribution Topologies
590(13)
19.3.1 Pre-Layout Design Considerations
590(12)
19.3.2 Design Considerations Based on Experimental Results
602(1)
19.4 Summary
603(2)
Chapter 20 3-D Circuit Architectures
605(44)
20.1 Classification of Wire Limited 3-D Circuits
606(1)
20.2 3-D Microprocessors and Memories
607(8)
20.2.1 3-D Microprocessor Logic Blocks
608(2)
20.2.2 3-D Design of Cache Memories
610(3)
20.2.3 Architecting a 3-D Microprocessor Memory System
613(2)
20.3 3-D Networks-on-Chip
615(24)
20.3.1 3-D NoC Topologies
616(1)
20.3.2 Zero-Load Latency for 3-D NoC
617(4)
20.3.3 Power Consumption in 3-D NoC
621(2)
20.3.4 Performance and Power Analysis for 3-D NoC
623(16)
20.4 3-D FPGAs
639(7)
20.5 Summary
646(3)
Chapter 21 Conclusions
649(4)
Appendix A Enumeration of Gate Pairs in a 3-D IC 653(2)
Appendix B Formal Proof of Optimum Single Via Placement 655(2)
Appendix C Proof of the Two-Terminal Via Placement Heuristic 657(2)
Appendix D Proof of Condition for Via Placement of Multi-terminal Nets 659(2)
Appendix E Correlation of WID Variations for Intratier Buffers 661(2)
Appendix F Extension of the Proposed Model to Include Variations of Wires 663(2)
Glossary of Terms 665(4)
References 669(40)
Index 709
Vasilis F. Pavlidis received the B.Sc. and M.Eng. degrees in Electrical and Computer Engineering from the Democritus University of Thrace, Greece, in 2000 and 2002, respectively. He received the M.Sc. and Ph.D. degrees in Electrical and Computer Engineering from the University of Rochester, Rochester, NY, in 2003 and 2008, respectively.He is currently an Assistant Professor in the School of Computer Science at the University of Manchester, Manchester, UK. From 2008 to 2012, he was a post-doctoral fellow with the Integrated Systems Laboratory at the Ecole Polytechnique Fédérale de Lausanne, Lausanne, Switzerland. He was with INTRACOM S.A., Athens, Greece, from 2000 to 2002. He has also been a visiting researcher at Synopsys Inc., Mountain View, CA, with the Primetime group in 2007. His current research interests include interconnect modeling and analysis, 3-D and 2.5-D integration, and other issues related to VLSI design. He has published several conference and journal papers in these areas. He was the leading designer of the Rochester cube and co-creator of the Manchester Thermal Analyzer.Dr. Pavlidis is on the editorial board of the Microelectronics Journal and Integration, the VLSI Journal. He also serves on the Technical Program Committees of several IEEE conferences. He is a member of the VLSI Systems & Applications Technical Committee of the Circuits and Systems Society and a member of the IEEE. He is also involved in public policy issues as a member of the ICT working group of the IEEE European Public Policy Initiative. Ioannis Savidis received the B.S.E. degree in electrical and computer engineering and biomedical engineering from Duke University, Durham, NC, in 2005. He received the M.Sc. and Ph.D. degrees in electrical and computer engineering from the University of Rochester, Rochester, NY, USA, in 2007 and 2013, respectively.He is currently an Assistant Professor with the Department of Electrical and Computer Engineering at Drexel University, Philadelphia, PA, USA, where he directs the Integrated Circuits and Electronics (ICE) Design and Analysis Laboratory. He has held visiting research positions with the 3-D Integration group at Freescale Semiconductor, Austin, TX, USA in 2007, and the System on Package and 3-D Integration group at the IBM T. J. Watson Research Center, Yorktown Heights, NY, in 2008, 2009, 2010, and 2011. His current research and teaching interests include analysis, modeling, and design methodologies for high performance digital and mixed-signal integrated circuits, power management for SoC and microprocessor circuits (including on-chip dc-dc converters), emerging integrated circuit technologies, IC design for trust (hardware security), and interconnect related issues in 2-D and 3-D ICs. He has authored or co-authored over 40 technical papers published in peer-reviewed journals and conferences, and holds 4 pending patents. Dr. Savidis is a member of the editorial boards of the IEEE Transactions on Very Large Scale Integration (VLSI) Systems, the Microelectronics Journal, and the Journal of Circuits, Systems and Computers. He serves on the Organizing Committees and Technical Program Committees of many international conferences including the IEEE International Symposium on Circuits and Systems, the Great Lakes Symposium on Very Large Scale Integration, the ACM/IEEE System Level Interconnect Prediction Workshop, and the IEEE International Symposium on Hardware Oriented Security and Trust. Eby G. Friedman received the B.S. degree from Lafayette College in 1979, and the M.S. and Ph.D. degrees from the University of California, Irvine, in 1981 and 1989, respectively, all in electrical engineering.

From 1979 to 1991, he was with Hughes Aircraft Company, rising to the position of manager of the Signal Processing Design and Test Department, responsible for the design and test of high performance digital and analog integrated circuits. He has been with the Department of Electrical and Computer Engineering at the University of Rochester since 1991, where he is a Distinguished Professor, and the Director of the High Performance VLSI/IC Design and Analysis Laboratory. He is also a Visiting Professor at the Technion - Israel Institute of Technology. His current research and teaching interests are in high performance synchronous digital and mixed-signal microelectronic design and analysis with application to high speed portable processors, low power wireless communications, and power efficient server farms.

He is the author of more than 500 papers and book chapters, 13 patents, and the author or editor of 18 books in the fields of high speed and low power CMOS design techniques, 3-D integration, high speed interconnect, and the theory and application of synchronous clock and power delivery and management. Dr. Friedman is the Editor-in-Chief of the Microelectronics Journal, a Member of the editorial board of the Journal of Low Power Electronics and Journal of Low Power Electronics and Applications, and a Member of the technical program committee of numerous conferences. He previously was the Editor-in-Chief and Chair of the Steering Committee of the IEEE Transactions on Very Large Scale Integration (VLSI) Systems, the Regional Editor of the Journal of Circuits, Systems and Computers, a Member of the editorial board of the Proceedings of the IEEE, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Analog Integrated Circuits and Signal Processing, and Journal of Signal Processing Systems, a Member of the Circuits and Systems (CAS) Society Board of Governors, Program and Technical chair of several IEEE conferences, and a recipient of the IEEE Circuits and Systems 2013 Charles A. Desoer Technical Achievement Award, a University of Rochester Graduate Teaching Award, and a College of Engineering Teaching Excellence Award. Dr. Friedman is an inaugural member of the University of California, Irvine Engineering Hall of Fame, a Senior Fulbright Fellow, and an IEEE Fellow.