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E-raamat: Domain Specific High-Level Synthesis for Cryptographic Workloads

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This book offers an in-depth study of the design and challenges addressed by a high-level synthesis tool targeting a specific class of cryptographic kernels, i.e. symmetric key cryptography. With the aid of detailed case studies, it also discusses optimization strategies that cannot be automatically undertaken by CRYKET (Cryptographic kernels toolkit. The dynamic nature of cryptography, where newer cryptographic functions and attacks frequently surface, means that such a tool can help cryptographers expedite the very large scale integration (VLSI) design cycle by rapidly exploring various design alternatives before reaching an optimal design option. Features include flexibility in cryptographic processors to support emerging cryptanalytic schemes; area-efficient multinational designs supporting various cryptographic functions; and design scalability on modern graphics processing units (GPUs). These case studies serve as a guide to cryptographers exploring the design of efficient cryptographic implementations.









 
1 Introduction
1(4)
1.1 Motivation
1(1)
1.2 Contributions and Structure of This Thesis
2(3)
References
4(1)
2 Background
5(18)
2.1 High Level Synthesis
6(8)
2.1.1 Motivation
6(2)
2.1.2 Generation Through Automation
8(1)
2.1.3 Steps of High Level Synthesis
9(2)
2.1.4 HLS: A Brief Retrospection
11(1)
2.1.5 The Current Generation of HLS
12(2)
2.2 High Level Synthesis for Cryptographic Workloads
14(1)
2.3 ASIC Design Flow Setup
15(4)
2.3.1 The Standard Cell Digital Design How
16(1)
2.3.2 ADL Based Design Flow
17(1)
2.3.3 Metrics
17(2)
2.4 Experimental Setup for CPU-GPGPUs Environment
19(1)
2.5 Concluding Remarks
19(4)
References
19(4)
3 Dwarfs of Cryptography
23(28)
3.1 Berkeley Dwarfs for Parallel Computing
23(1)
3.2 Cryptology Background
24(4)
3.2.1 Block Ciphers
25(1)
3.2.2 Stream Ciphers
26(1)
3.2.3 Hash Functions
27(1)
3.3 Block Ciphers: Major Ingredient of Symmetric Key Cryptography
28(3)
3.3.1 Transformations Under Modes Of Operation
28(2)
3.3.2 Basic Building Blocks for Symmetric Key Cryptography
30(1)
3.4 Cipher Algorithmic Configuration Space
31(15)
3.4.1 Block Ciphers
31(6)
3.4.2 Stream Ciphers
37(8)
3.4.3 Hash Functions
45(1)
3.5 Concluding Remarks
46(5)
References
46(5)
4 High Level Synthesis for Symmetric Key Cryptography
51(40)
4.1 CRYKET (CRYptographic Kernels Toolkit)
52(1)
4.2 RunFein
53(18)
4.2.1 Design Specification Compilation
53(1)
4.2.2 Specification Validation and Formal Model Creation
54(3)
4.2.3 Software Generation Engine
57(1)
4.2.4 Hardware Generation Engine
58(5)
4.2.5 Results and Analysis: Software Efficiency
63(1)
4.2.6 Results and Analysis: Hardware Efficiency
64(7)
4.3 RunStream
71(18)
4.3.1 Design Specification Compilation
72(1)
4.3.2 Specification Validation and Formal Model Creation
73(3)
4.3.3 Software Generation Engine
76(2)
4.3.4 Hardware Generation Engine
78(4)
4.3.5 Efficiency
82(4)
4.3.6 Comparison with Manual Implementations
86(3)
4.4 Concluding Remarks
89(2)
References
89(2)
5 Manual Optimizations for Efficient Designs
91(36)
5.1 Optimization Strategies
91(1)
5.1.1 Memory Bank Structure Optimizations
91(1)
5.1.2 Unification of Multiple Cryptographic Proposals
91(1)
5.2 Memory Bank Structure Optimizations
92(15)
5.2.1 Reviewing Known Techniques
93(1)
5.2.2 Optimized Memory Utilization for HC-128
93(1)
5.2.3 Design Space Exploration of HC-128 Accelerator
94(4)
5.2.4 State Split Optimizations for HC-128
98(6)
5.2.5 Performance Evaluation
104(3)
5.3 Integrated Implementation of Multiple Cryptographic Primitives
107(16)
5.3.1 Motivation
107(1)
5.3.2 Previous Work
107(1)
5.3.3 Contribution: HiPAcc-LTE-Integrated Accelerator for SNOW 3G and ZUC
107(1)
5.3.4 Structural Comparison
108(2)
5.3.5 Integrating the Main LFSR
110(1)
5.3.6 Integrating the FSM
111(4)
5.3.7 ASIC Implementation of HiPAcc-LTE
115(8)
5.4 Concluding Remarks
123(4)
References
124(3)
6 Study of Flexibility
127(42)
6.1 Motivation
127(1)
6.2 Contribution
128(1)
6.3 CoARX: A Coprocessor for ARX-Based Cryptographic Algorithms
129(14)
6.3.1 Related Work
129(3)
6.3.2 Design Space Exploration
132(4)
6.3.3 Mapping of the ARX Algorithms
136(4)
6.3.4 Implementation and Benchmarking
140(3)
6.4 RC4-AccSuite: A Hardware Acceleration Suite for RC4-like Stream Ciphers
143(22)
6.4.1 RC4 Stream Cipher Algorithm
144(1)
6.4.2 Variants of RC4
144(2)
6.4.3 Contribution
146(1)
6.4.4 High-Level Architecture of RC4-AccSuite
146(2)
6.4.5 Performance Enhancement by Memory Replication Technique
148(4)
6.4.6 Resource Economization in RC4-AccSuite
152(6)
6.4.7 Implementation and Benchmarking
158(7)
6.5 Concluding Remarks
165(4)
References
166(3)
7 Study of Scalability
169(26)
7.1 Motivation
169(1)
7.2 Major Contributions
170(1)
7.3 The Compute Unified Device Architecture (CUDA) Overview
170(2)
7.3.1 Kernel Execution Model
171(1)
7.3.2 Memory Model
172(1)
7.4 Block Ciphers Performance Acceleration on GPUs
172(1)
7.5 Mapping Salsa20 Stream Cipher on GPUs
173(11)
7.5.1 Analyzing Parallelism Opportunities of Salsa20
173(1)
7.5.2 Batch Processing Framework
174(2)
7.5.3 CUDA Coding Guidelines
176(1)
7.5.4 Optimization for Salsa20
177(1)
7.5.5 Autotuning for Throughput Optimization
177(3)
7.5.6 Results and Analysis
180(4)
7.6 Mapping HC-128 Stream Cipher on GPUs
184(10)
7.6.1 Hurdles in Parallelization of HC Ciphers
185(2)
7.6.2 Optimization Strategies
187(3)
7.6.3 Experimental Analysis
190(4)
7.7 Concluding Remarks
194(1)
References
194(1)
8 Efficient Cryptanalytic Hardware
195(20)
8.1 Introduction
195(1)
8.2 Background
196(1)
8.2.1 Attacks Against SHA-1
196(1)
8.2.2 Reported Hardware Attacks
197(1)
8.3 Cracken
197(10)
8.3.1 Attack Algorithm
197(2)
8.3.2 Kraken Architecture
199(8)
8.4 Performance Analysis and Comparisons
207(5)
8.4.1 Synthesis Results
207(1)
8.4.2 Physical Synthesis
207(1)
8.4.3 Cost-Performance Approximation with Memories
208(2)
8.4.4 Power Consumption Aggregates
210(1)
8.4.5 Mapping Kraken on FPGAs
210(1)
8.4.6 Comparison with Other Implementations
210(2)
8.5 Concluding Remarks
212(3)
References
213(2)
9 Conclusion and Future Work
215(4)
9.1 Outlook
216(3)
Appendix A RunFein Generated AES-128 Code 219(2)
Appendix B RunFein GUI Snapshots 221(2)
Appendix C Description of Some ARX Based Cryptographic Functions 223(12)
Appendix D Overview of SNOW 3G and ZUC Stream Ciphers 235
Ayesha Khalid completed her B.E. in Computer Systems Engineering from National University of Sciences and Technology (NUST), Pakistan. She did her M.S. in Electrical Engineering from Center for Advanced Studies in Engineering (CASE), affiliated with University of Engineering and Technology, UET-Taxila, Pakistan. From 2000 to 2010, she served as a Lecturer in the Department of Electrical Engineering at Muhammad Ali Jinnah University, Islamabad and later joined RWTH Aachen, Germany as a Research Associate for her doctoral studies. She is the recipient of DAAD scholarship award for Ph.D. Her dissertation focuses on the identification, characterization and exploitation of representative cryptographic operations/ structures for a whole class of cryptography, enabling high-level synthesis of cryptographic proposals. Currently, she is working as a Research Fellow at Queens University Belfast (QUB) in the SAFECrypto project.

Goutam Paul completed his undergraduate in Computer Engineering in 2001 from Bengal Engineering College (Deemed University), now Indian Institute of Engineering Science and Technology (IIEST), Shibpur, Howrah,  India; Master degree in Computer Science in 2003 from State University of New York (SUNY) at Albany, U.S.A.; and Ph.D. in Cryptology in 2009 from Indian Statistical Institute, Kolkata (degree awarded from Jadavpur University, Kolkata, India).From 2006 to 2013, he was an Assistant Professor in the Department of Computer Science and Engineering of Jadavpur University and during 2012-2013, he visited RWTH Aachen, Germany as a Humboldt Fellow. From August 2013, Goutam Paul has been serving the R. C. Bose Centre for Cryptology and Security of Indian Statistical Institute, Kolkata, as an Assistant Professor. He also received the Young Scientist Award from the National Academy of Sciences, India (NASI) in 2013. His doctoral research focussed on the analysis of RC4, the then most popular and most widely commercially deployed software stream cipher and also the then standard encryption tool for IEEE WiFi protocol; and his work revealed many critical weaknesses of the cipher and initiated a chain of subsequent research by others in this area. Later he also worked on the analysis of other stream ciphers like HC-128, Grain-v1, Salsa20. Recently, he has taken up keen interest in efficient hardware design of cryptographic primitives and in the analysis of BB84-like quantum key distribution protocols. Goutam Paul is the author of one book and more than 60 papers in peer-reviewed international journals and conferences. He regularly serves as the TPC member of many top conferences, reviewer of many premier journals and presents invited seminars in internationally acclaimed venues. He is a member of ACM and a senior member of IEEE.

Anupam Chattopadhyay received his B.E. degree from Jadavpur University, India in 2000. He received his MSc. from ALaRI, Switzerland and PhD from RWTH Aachen in 2002 and 2008 respectively.From 2008 to 2009, he worked as a Member of Consulting Staff in CoWare R&D, Noida, India. From 2010 to 2014, he led the MPSoC Architectures Research Group in RWTH Aachen, Germany as a Junior Professor. Since September, 2014, he is appointed as an assistant Professor in SCE, NTU. During his PhD, he worked on automatic RTL generation from the architecture description language LISA, which was commercialized later by a leading EDA vendor. He developed several high-level optimizations and verification flow for embedded processors. In his doctoral thesis, he proposed a language-based modeling, exploration and implementation framework for partially re-configurable processors. Together with his doctoral students, he proposed domain-specific high-level synthesis for cryptography, high-level reliability estimation flows, generalization of classic linear algebra kernels and a novel multi-layered coarse-grained reconfigurable architecture. In these areas, he published as a (co)-author over 80 conference/ journal papers, several book-chapters and a book. Anupam served in several TPCs of top conferences, regularly reviews journal/ conference articles and presented multiple invited seminars/tutorials in prestigious venues. He is a member of ACM and a senior member of IEEE.