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E-raamat: EDA for IC System Design, Verification, and Testing

Edited by (Cadence Design Systems, San Jose, California, USA), Edited by (Cadence Berkeley Laboratories, California, USA), Edited by (Tensilica Inc., Santa Clara, California, USA)
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Volume one of this set covers system-level design, micro-architectural design, verification, and testing while volume two addresses analog and mixed-signal design, physical verification, analysis and extraction, and CAD. The 23 chapters describe the various tools, models, and languages available for systems-on-chip design, processors, embedded software, power management, and automatic test pattern generation. Topics include the Architecture description language, processor performance benchmarks, VHDL and Verilog, intellectual property reuse, transaction-level models, jitter measurement techniques, and formal property checking. Annotation ©2006 Book News, Inc., Portland, OR (booknews.com)

Presenting a comprehensive overview of the design automation algorithms, tools, and methodologies used to design integrated circuits, the Electronic Design Automation for Integrated Circuits Handbook is available in two volumes. The first volume, EDA for IC System Design, Verification, and Testing, thoroughly examines system-level design, microarchitectural design, logical verification, and testing. Chapters contributed by leading experts authoritatively discuss processor modeling and design tools, using performance metrics to select microprocessor cores for IC designs, design and verification languages, digital simulation, hardware acceleration and emulation, and much more. Save on the complete set.
SECTION I Introduction
1 Overview
Luciano Lavagno, Grant Martin, and Louis Scheffer
1-1(1)
Introduction to Electronic Design Automation for Integrated Circuits
1-2(1)
System Level Design
1-6(1)
Micro-Architecture Design
1-8(1)
Logical Verification
1-8(1)
Test
1-9(1)
RTL to GDS-II, or Synthesis, Place, and Route
1-9(1)
Analog and Mixed-Signal Design
1-11(1)
Physical Verification
1-11(1)
Technology Computer-Aided Design
1-12(1)
2 The Integrated Circuit Design Process and Electronic Design Automation
Robert Damiano and Raul Camposano
2-1(1)
2.1 Introduction
2-1(1)
2.2 Verification
2-3(1)
2.3 Implementation
2-5(1)
2.4 Design for Manufacturing
2-11(1)
SECTION II System Level Design
3 Tools and Methodologies for System-Level Design
Shuvra Bhattacharyya and Wayne Wolf
3-1(1)
3.1 Introduction
3-1(1)
3.2 Characteristics of Video Applications
3-2(1)
3.3 Other Application Domains
3-3(1)
3.4 Platform Characteristics
3-3(1)
3.5 Models of Computation and Tools for Model-Based Design
3-6(1)
3.6 Simulation
3-13(1)
3.7 Hardware/Software Cosynthesis
3-14(1)
3.8 Summary
3-15(1)
4 System-Level Specification and Modeling Languages
Joseph T. Buck
4-1(1)
4.1 Introduction
4-1(1)
4.2 A Survey of Domain-Specific Languages and Methods
4-2(1)
4.3 Heterogeneous Platforms and Methodologies
4-12(1)
4.4 Conclusions
4-13(1)
5 SoC Block-Based Design and IP Assembly
John Wilson
5-1(1)
5.1 The Economics of Reusable IP and Block-Based Design
5-2(1)
5.2 Standard Bus Interfaces
5-3(1)
5.3 Use of Assertion-Based Verification
5-4(1)
5.4 Use of IP Configurators and Generators
5-5(1)
5.5 The Design Assembly and Verification Challenge
5-7(1)
5.6 The SPIRIT XML Databook Initiative
5-8(1)
5.7 Conclusions
5-10(1)
6 Performance Evaluation Methods for Multiprocessor System-on-Chip Design
Ahmed Jerraya and Iuliana Bacivarov
6-1(1)
6.1 Introduction
6-1(1)
6.2 Overview of Performance Evaluation in the Context of System Design Flow
6-2(1)
6.3 MPSoC Performance Evaluation
6-9(1)
6.4 Conclusion
6-12(1)
7 System-Level Power Management
Naehyuck Chang, Enrico Macii, Massimo Poncino, and Vivek Tiwari
7-1(1)
7.1 Introduction
7-1(1)
7.2 Dynamic Power Management
7-2(1)
7.3 Battery-Aware Dynamic Power Management
7-10(1)
7.4 Software-Level Dynamic Power Management
7-13(1)
7.5 Conclusions
7-17(1)
8 Processor Modeling and Design Tools
Prabhat Mishra and Nikil Dutt
8-1(1)
8.1 Introduction
8-1(1)
8.2 Processor Modeling Using ADLs
8-2(1)
8.3 ADL-Driven Methodologies
8-11(1)
8.4 Conclusions
8-18(1)
9 Embedded Software Modeling and Design
Marco Di Natale
9-1(1)
9.1 Introduction
9-1(1)
9.2 Synchronous vs. Asynchronous Models
9-13(1)
9.3 Synchronous Models
9-13(1)
9.4 Asynchronous Models
9-16(1)
9.5 Research on Models for Embedded Software
9-34(1)
9.6 Conclusions
9-40(1)
10 Using Performance Metrics to Select Microprocessor Cores for IC Designs
Steve Leibson
10-1(1)
10.1 Introduction
10-1(1)
10.2 The ISS as Benchmarking Platform
10-3(1)
10.3 Ideal Versus Practical Processor Benchmarks
10-4(1)
10.4 Standard Benchmark Types
10-4(1)
10.5 Prehistoric Performance Ratings: MIPS, MOPS, and MFLOPS
10-5(1)
10.6 Classic Processor Benchmarks (The Stone Age)
10-6(1)
10.7 Modern Processor Performance Benchmarks
10-13(1)
10.8 Configurable Processors and the Future of Processor-Core Benchmarks
10-22(1)
10.9 Conclusion
10-25(1)
11 Parallelizing High-Level Synthesis: A Code Transformational Approach to High-Level Synthesis
Gaurav Singh, Sumit Gupta, Sandeep Shukla, and Rajesh Gupta
11-1(1)
11.1 Introduction
11-2(1)
11.2 Background and Survey of the State of the Art
11-3(1)
11.3 Parallelizing HLS
11-11(1)
11.4 The SPARK PHLS Framework
11-15(1)
11.5 Summary
11-16(1)
SECTION III Micro-Architecture Design
12 Cycle-Accurate System-Level Modeling and Performance Evaluation
Marcello Coppola and Miltos D. Grammatikakis
12-1(1)
12.1 Introduction
12-1(1)
12.2 System Modeling and Design Methodology
12-3(1)
12.3 Back-Annotation of System-Level Modeling Objects
12-6(1)
12.4 Automatic Extraction of Statistical Features
12-10(1)
12.5 Open System-Level Modeling Issues
12-16(1)
13 Micro-Architectural Power Estimation and Optimization
Enrico Macii, Renu Mehra, and Massimo Poncino
13-1(1)
13.1 Introduction
13-1(1)
13.2 Background
13-2(1)
13.3 Architectural Template
13-4(1)
13.4 Micro-Architectural Power Modeling and Estimation
13-5(1)
13.5 Micro-Architectural Power Optimization
13-14(1)
13.6 Conclusions
13-29(1)
14 Design Planning
Ralph H.J.M. Otten
14-1(1)
14.1 Introduction
14-1(1)
14.2 Floorplans
14-3(1)
14.3 Wireplans
14-9(1)
14.4 A Formal System For Trade-Offs
14-17(1)
SECTION IV Logical Verification
15 Design and Verification Languages
Stephen A. Edwards
15-1(1)
15.1 Introduction
15-1(1)
15.2 History
15-2(1)
15.3 Design Languages
15-3(1)
15.4 Verification Languages
15-16(1)
15.5 Conclusions
15-26(1)
16 Digital Simulation
John Sanguinetti
16-1(1)
16.1 Introduction
16-1(1)
16.2 Event- vs. Process-Oriented Simulation
16-3(1)
16.3 Logic Simulation Methods and Algorithms
16-3(1)
16.4 Impact of Languages on Logic Simulation
16-11(1)
16.5 Logic Simulation Techniques
16-13(1)
16.6 Impact of HVLs on Simulation
16-16(1)
16.7 Summary
16-16(1)
17 Using Transactional-Level Models in an SoC Design Flow
Alain Clouard, Frank Ghenassia, Laurent Maillet-Contoz, and Jean-Philippe Strassen
17-1(1)
17.1 Introduction
17-1(1)
17.2 Related Work
17-2(1)
17.3 Overview of the System-to-RTL Design Flow
17-4(1)
17.4 TLM-A Complementary View for the Design Flow
17-6(1)
17.5 TLM Modeling Application Programming Interface
17-11(1)
17.6 Example of a Multimedia Platform
17-13(1)
17.7 Design Flow Automation
17-15(1)
17.8 Conclusion
17-17(1)
18 Assertion-Based Verification
Erich Marschner and Harry Foster
18-1(1)
18.1 Introduction
18-1(1)
18.2 History
18-2(1)
18.3 State of the Art
18-8(1)
19 Hardware Acceleration and Emulation
Ray Turner and Mike Bershteyn
19-1(1)
19.1 Introduction
19-1(1)
19.2 Emulator Architecture Overview
19-4(1)
19.3 Design Modeling
19-9(1)
19.4 Debugging
19-14(1)
19.5 Use Models
19-15(1)
19.6 The Value of In-Circuit Emulation
19-17(1)
19.7 Considerations for Successful Emulation
19-17(1)
19.8 Summary
19-20(1)
20 Formal Property Verification
Limor Fix and Ken McMillan
20-1(1)
20.1 Introduction
20-1(1)
20.2 Formal Property Verification Methods and Technologies
20-4(1)
20.3 Software Formal Verification
20-8(1)
20.4 Summary
20-11(1)
SECTION V Test
21 Design-For-Test
Bernd Koenemann
21-1(1)
21.1 Introduction
21-1(1)
21.2 The Objectives of Design-For-Test for Microelectronics Products
21-2(1)
21.3 Overview of Chip-Level Design-For-Test Techniques
21-5(1)
21.4 Conclusion
21-33(1)
22 Automatic Test Pattern Generation
Kwang-Ting (Tim) Cheng and Li-C. Wang
22-1(1)
22.1 Introduction
22-1(1)
22.2 Combinational ATPG
22-2(1)
22.3 Sequential ATPG
22-7(1)
22.4 ATPG and SAT
22-13(1)
22.5 Applications of ATPG
22-20(1)
22.6 High-Level ATPG
22-25(1)
23 Analog and Mixed Signal Test
Bozena Kaminska
23-1
23.1 Introduction
23-1(1)
23.2 Analog Circuits and Analog Specifications
23-2(1)
23.3 Testability Analysis
23-4(1)
23.4 Fault Modeling and Test Specification
23-5(1)
23.5 Catastrophic Fault Modeling and Simulation
23-6(1)
23.6 Parametric Faults, Worst-Case Tolerance Analysis, and Test Generation
23-6(1)
23.7 Design for Test An Overview
23-7(1)
23.8 Analog Test Bus Standard
23-7(1)
23.9 Oscillation-Based DFT/BIST
23-8(1)
23.10 PLL, VCO, and Jitter Testing
23-10(1)
23.11 Review of Jitter Measurement Techniques
23-11(1)
23.12 Summary
23-22
Index
Louis Scheffer, Luciano Lavagno, Grant Martin
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