This book describes new and effective methodologies for modeling, analyzing and mitigating cell-internal signal electromigration in nanoCMOS, with significant circuit lifetime improvements and no impact on performance, area and power. The authors are the first to analyze and propose a solution for the electromigration effects inside logic cells of a circuit. They show in this book that an interconnect inside a cell can fail reducing considerably the circuit lifetime and they demonstrate a methodology to optimize the lifetime of circuits, by placing the output, Vdd and Vss pin of the cells in the less critical regions, where the electromigration effects are reduced. Readers will be enabled to apply this methodology only for the critical cells in the circuit, avoiding impact in the circuit delay, area and performance, thus increasing the lifetime of the circuit without loss in other characteristics.
Chapter 1. Introduction.- Chapter 2. State of the Art.- Chapter 3. Modeling Cell-internal EM.- Chapter 4. Current Calculation.- Chapter 5. Experimental Setup.- Chapter 6.Results.- Chapter 7. Analyzing the Electromigration Effects on Different Metal Layers.- Chapter 8. Conclusions.
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1 | (10) |
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1.1 Reliability and Electromigration |
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1.2 Electromigration in Future Technologies |
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1.3 Motivation and Contributions |
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2.1 Mitigating the EM Effects in Different IC Design Flow Stages |
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2.1.1 Managing Electromigration in Logic Designs |
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2.1.2 Electromigration Impact in Future Technologies |
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2.1.3 Smart Non-default Routing for Clock Power Reduction |
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2.1.4 Impacts of Electromigration Awareness |
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2.2 Mitigating the EM Effects in Different Types of Interconnections... |
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2.2.2 Power Delivery Network |
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2.2.5 Signal Interconnects |
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2.3 Summary of Related Works |
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3 Modeling Cell-Internal EM |
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3.1 Modeling Time-to-Failure Under EM |
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3.2.1 Local Hot Spots from Joule Heating |
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3.3.1 New Electromigration Validation: Via Node Vector Method |
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3.3.2 Applying Current Divergence in the Proposed EM Model |
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3.3.3 The Impact of Blech Length on Cell-Internal Interconnects |
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4.1 Current Flows Using Graph Traversals |
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4.2 Algebra for Average/RMS Current Updates |
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4.2.1 Algebra for Computing Average Current |
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4.2.2 Algebra for Computing the RMS Current |
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6.1 The Electromigration Effects for Different Logic Gates |
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6.1.1 NAND2_X2 and NOR2_X2 Gates |
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7 Analyzing the Electromigration Effects on Different Metal Layers and Different Wire Lengths |
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| A Impact on Physical Synthesis Considering Different Amounts of Instances with EM Awareness |
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| B Coupling Capacitance Currents |
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| References |
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Gracieli Posser is a post-doctoral researcher at Universidade Federal do Rio Grande do Sul (UFRGS) and Inter-Software Engineer at Cadence Design Systems - Austin, TX.
Sachin S. Sapatnekar holds the Distinguished McKnight University Professorship and the Robert and Marjorie Henle Chair in Electrical and Computer Engineering at the University of Minnesota. He has authored nine books and numerous papers in this area and has received six conference Best Paper Awards and a Best Poster Award, as well as the ICCAD Ten-Year Retrospective Most Influential Paper Award, an award that recognizes a paper that has had a significant impact ten years after its publication. Dr. Sapatnekar has served as the Editor-in-Chief of the IEEE Transactions on Computer Aided Design and as General Chair for the ACM/IEEE Design Automation Conference, the two top publication venues in his research area, as well as leadership roles (General Chair and/or Technical Program Chair) in the ACM International Symposium on Physical Design, the IEEE/ACM Tau Workshop, and the International Conference on VLSI Design. He was conferred with a Fulbright award as a Senior Researcher in Spain in the Fall of 2013, and held the D.J. Gandhi Visiting Professorship at IIT Bombay in early 2014. He has received the NSF Career Award and the Semiconductor Research Corporation Technical Excellence Award, and he is a Fellow of the IEEE.
Ricardo Reis is Full Professor at Instituto de Informatica of the Universidade Federal do Rio Grande do Sul - UFRGS (professor since 1979). Electrical Engineering from the UFRGS, Porto Alegre, Brazil, in 1978. Ph.D. degree from the Polytechnic Institute of Grenoble (INPG), France, January 1983. Member of the Microelectronics Committee of National Council for Scientific and Technological Development (CNPq). Former member of the Computer Science Committee of National Council for Scientific and Technological Development (CNPq), for two terms. His primary research interests include Physical Design Automation and Methodologies, CAD tools, Circuits Tolerant to Radiation, VLSI Design Methodologies and Microelectronics Education. More than 350 hundred papers in journals and conferences proceedings. He is also author or co-author of several books. Invited speaker in several international conferences. Award as research of the year by the Science Foundation of Rio Grande do Sul, 2002. Silver Core award from IFIP. Research level 1A of the CNPq (Brazilian National Science Foundation). Head of several research projects. Past head of the Graduate Program in Microelectronics (2 terms) and of Computer Science Graduate Program at UFRGS (two terms). Professor and advisor at the Microelectronics and Computer Science Graduate Programs at UFRGS. General Chair or Program Chair of several conferences like the IFIP/IEEE VLSI-SoC, IEEE ISVLSI, IEEE LASCAS, Symposium on Integrated Circuits and Systems Design (SBCCI) and Congress of the Brazilian Microelectronics Society (SBMIcro). Past President of the Brazilian Computer Society and Past Vice-President of the Brazilian Microelectronics Society. IEEE CASS Chapter Rio Grande do Sul Chair (since 2007). Vice-president of IEEE Circuits and Systems representing R9, for two terms, from 2008 to 2011. Member of the Editorial Board of IEEE Design&Test. Member of the Steering Committee of the following conferences: IFIP/IEEE VLSI-SoC, ICECS, LASCAS, NEWCAS, IEEE CASS Summer School, IEEE ISVLSI, SBCCI, IBERCHIP. Senior member of IEEE.
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