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E-raamat: Embedded Multiprocessors: Scheduling and Synchronization, Second Edition

(Texas Instruments, Palo Alto, California, USA), (University of Maryland, College Park, USA)
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Techniques for Optimizing Multiprocessor Implementations of Signal Processing Applications

An indispensable component of the information age, signal processing is embedded in a variety of consumer devices, including cell phones and digital television, as well as in communication infrastructure, such as media servers and cellular base stations. Multiple programmable processors, along with custom hardware running in parallel, are needed to achieve the computation throughput required of such applications.

Reviews important research in key areas related to the multiprocessor implementation of multimedia systemsEmbedded Multiprocessors: Scheduling and Synchronization, Second Edition presents architectures and design methodologies for parallel systems in embedded digital signal processing (DSP) applications. It discusses application modeling techniques for multimedia systems, the incorporation of interprocessor communication costs into multiprocessor scheduling decisions, and a modeling methodology (the synchronization graph) for multiprocessor system performance analysis. The book also applies the synchronization graph model to develop hardware and software optimizations that can significantly reduce the interprocessor communication overhead of a given schedule.

Chronicles recent activity dealing with single-chip multiprocessors and dataflow modelsThis edition updates the background material on existing embedded multiprocessors, including single-chip multiprocessors. It also summarizes the new research on dataflow models for signal processing that has been carried out since the publication of the first edition.

Harness the power of multiprocessorsThis book explores the optimization of interprocessor communication and synchronization in embedded multiprocessor systems. It shows you how to design multiprocessor computer systems that are streamlined for multimedia applications.

Arvustused

"While some of the methods [ this book] describes are relatively simple, most are quite sophisticated. Yet examples are given that concretely demonstrate how these concepts can be applied in practical hardware architectures. Moreover, there is very little overlap with other books on parallel processing. The focus on application-specific processors and their use in embedded systems leads to a rather different set of techniques. I believe that this book defines a new discipline. It gives a systematic approach to problems that engineers previously have been able to tackle only in an ad hoc manner." Edward A. Lee, University of California, Berkeley, USA

Introduction
1(12)
Multiprocessor DSP Systems
2(2)
Application-Specific Multiprocessors
4(1)
Exploitation of Parallelism
5(1)
Dataflow Modeling for DSP Design
6(3)
Utility of Dataflow for DSP
9(2)
Overview
11(2)
Application-Specific Multiprocessors
13(22)
Parallel Architecture Classifications
13(2)
Exploiting Instruction Level Parallelism
15(5)
ILP in Programmable DSP Processors
15(2)
Subword Parallelism
17(1)
VLIW Processors
18(2)
Dataflow DSP Architectures
20(1)
Systolic and Wavefront Arrays
20(1)
Multiprocessor DSP Architectures
21(2)
Single-Chip Multiprocessors
23(7)
The MathStar MP-SOC
24(1)
The Ambric Processor
24(1)
The Stream Processor
25(1)
Graphics Processors
25(1)
The Sandbridge Sandblaster
26(1)
picoChip
26(1)
Single-Chip Multiprocessors from Texas Instruments
27(2)
The Tilera Processor
29(1)
Heterogeneous Multiprocessors
29(1)
Reconfigurable Computing
30(2)
Architectures that Exploit Predictable IPC
32(2)
Summary
34(1)
Background Terminology and Notation
35(24)
Graph Data Structures
35(1)
Dataflow Graphs
36(1)
Computation Graphs
37(1)
Petri Nets
37(1)
Synchronous Dataflow
38(1)
Analytical Properties of SDF Graphs
39(1)
Converting a General SDF Graph into a Homogeneous SDF Graph
40(2)
Acyclic Precedence Expansion Graph
42(2)
Application Graph
44(1)
Synchronous Languages
44(3)
HSDFG Concepts and Notations
47(2)
Complexity of Algorithms
49(2)
Shortest and Longest Paths in Graphs
51(3)
Dijkstra's Algorithm
52(1)
The Bellman-Ford Algorithm
52(1)
The Floyd-Warshall Algorithm
52(2)
Solving Difference Constraints Using Shortest Paths
54(2)
Maximum Cycle Mean
56(1)
Summary
57(2)
DSP-Oriented Dataflow Models of Computation
59(26)
Scalable Synchronous Dataflow
60(2)
Cyclo-Static Dataflow
62(5)
Lumped SDF Representations
63(3)
Phase Repetitions Vectors
66(1)
Equivalent HSDF Graphs
66(1)
Analysis Techniques
67(1)
Multidimensional Synchronous Dataflow
67(4)
Parameterized Dataflow
71(2)
Reactive Process Networks
73(1)
Integrating Dataflow and State Machine Models
74(4)
CAL
75(1)
FunState
76(1)
Starcharts and Heterochronous Dataflow
76(1)
DF-STAR
77(1)
DFCharts
78(1)
Controlled Dataflow Actors
78(5)
Boolean Dataflow
78(1)
Stream-Based Functions
79(4)
Enable-Invoke Dataflow
83(1)
Summary
83(2)
Multiprocessor Scheduling Models
85(20)
Task-Level Parallelism and Data Parallelism
85(1)
Static versus Dynamic Scheduling Strategies
86(1)
Fully-Static Schedules
87(5)
Self-Timed Schedules
92(2)
Dynamic Schedules
94(1)
Quasi-Static Schedules
94(1)
Schedule Notation
95(4)
Unfolding HSDF Graphs
99(2)
Execution Time Estimates and Static Schedules
101(3)
Summary
104(1)
IPC-Conscious Scheduling Algorithms
105(26)
Problem Description
105(1)
Stone's Assignment Algorithm
106(4)
List Scheduling Algorithms
110(7)
Graham's Bounds
111(3)
The Basic Algorithms --- HLFET and ETF
114(1)
The Mapping Heuristic
114(1)
Dynamic Level Scheduling
115(1)
Dynamic Critical Path Scheduling
116(1)
Clustering Algorithms
117(5)
Linear Clustering
118(1)
Internalization
119(1)
Dominant Sequence Clustering
119(1)
Declustering
120(2)
Integrated Scheduling Algorithms
122(2)
Pipelined Scheduling
124(5)
Summary
129(2)
The Ordered-Transactions Strategy
131(34)
The Ordered-Transactions Strategy
131(2)
Shared Bus Architecture
133(1)
Interprocessor Communication Mechanisms
134(3)
Using the Ordered-Transactions Approach
137(1)
Design of an Ordered Memory Access Multiprocessor
138(4)
High Level Design Description
138(1)
A Modified Design
139(3)
Design Details of a Prototype
142(13)
Top Level Design
142(2)
Transaction Order Controller
144(5)
Host Interface
149(1)
Processing Element
150(1)
FPGA Circuitry
151(3)
Shared Memory
154(1)
Connecting Multiple Boards
154(1)
Hardware and Software Implementation
155(2)
Board Design
155(1)
Software Interface
156(1)
Ordered I/O and Parameter Control
157(2)
Application Examples
159(3)
Music Synthesis
159(1)
QMF Filter Bank
159(3)
1024 Point Complex Fast Fourier Transform (FFT)
162(1)
Summary
162(3)
Analysis of the Ordered-Transactions Strategy
165(24)
Inter-processor Communication Graph (Gipc)
168(5)
Execution Time Estimates
173(1)
Ordering Constraints Viewed as Added Edges
174(1)
Periodicity
175(1)
Optimal Order
176(3)
Effects of Changes in Execution Times
179(7)
Deterministic Case
180(2)
Modeling Run-time Variations in Execution Times
182(2)
Bounds on the Average Iteration Period
184(1)
Implications for the Ordered Transactions Schedule
185(1)
Effects of Interprocessor Communication Costs
186(2)
Summary
188(1)
Extending the OMA Architecture
189(16)
Scheduling BDF Graphs
189(2)
Parallel Implementation on Shared Memory Machines
191(11)
General Strategy
191(3)
Implementation on the OMA
194(2)
Improved Mechanism
196(3)
Generating the Annotated Bus Access List
199(3)
Data-dependent Iteration
202(1)
Summary
203(2)
Synchronization in Self-Timed Systems
205(36)
The Barrier MIMD Technique
206(1)
Redundant Synchronization Removal in Non-Iterative Dataflow
207(3)
Analysis of Self-Timed Execution
210(1)
Estimated Throughput
210(1)
Strongly Connected Components and Buffer Size Bounds
210(3)
Synchronization Model
213(5)
Synchronization Protocols
213(2)
The Synchronization Graph
215(3)
A Synchronization Cost Metric
218(1)
Removing Redundant Synchronizations
219(6)
The Independence of Redundant Synchronizations
220(1)
Removing Redundant Synchronizations
221(2)
Comparison with Shaffer's Approach
223(1)
An Example
223(2)
Making the Synchronization Graph Strongly Connected
225(4)
Adding Edges to the Synchronization Graph
227(2)
Insertion of Delays
229(10)
Analysis of DetermineDelays
231(3)
Delay Insertion Example
234(2)
Extending the Algorithm
236(1)
Complexity
237(1)
Related Work
238(1)
Summary
239(2)
Resynchronization
241(32)
Definition of Resynchronization
241(2)
Properties of Resynchronization
243(3)
Relationship to Set Covering
246(3)
Intractability of Resynchronization
249(3)
Heuristic Solutions
252(12)
Applying Set Covering Techniques to Pairs of SCCs
252(3)
A More Flexible Approach
255(4)
Unit-Subsumption Resynchronization Edges
259(2)
Example
261(2)
Simulation Approach
263(1)
Chainable Synchronization Graphs
264(6)
Chainable Synchronization Graph SCCs
264(2)
Comparison to the Global-Resynchronize Heuristic
266(2)
A Generalization of the Chaining Technique
268(1)
Incorporating the Chaining Technique
268(2)
Resynchronization of Constraint Graphs for Relative Scheduling
270(1)
Summary
271(2)
Latency-Constrained Resynchronization
273(46)
Elimination of Synchronization Edges
274(1)
Latency-Constrained Resynchronization
275(6)
Intractability of LCR
281(7)
Two-Processor Systems
288(16)
Interval Covering
289(1)
Two-Processor Latency-Constrained Resynchronization
289(4)
Taking Delays into Account
293(11)
A Heuristic for General Synchronization Graphs
304(11)
Customization to Transparent Synchronization Graphs
305(2)
Complexity
307(1)
Example
308(7)
Summary
315(4)
Integrated Synchronization Optimization
319(6)
Computing Buffer Sizes
319(1)
A Framework for Self-Timed Implementation
320(2)
Summary
322(3)
Future Research Directions
325(4)
Bibliography 329(24)
Index 353(8)
About the Authors 361
Sundararajan Sriram, Shuvra S. Bhattacharyya
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