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E-raamat: Energy Efficient Hardware-Software Co-Synthesis Using Reconfigurable Hardware

(University of Southern California, Los Angeles, USA), (Xilinix, San Jose, CA, USA)
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Energy Efficient Hardware-Software Co-Synthesis Using Reconfigurable HardwareSuurem pilt
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Rapid energy estimation for energy efficient applications using field-programmable gate arrays (FPGAs) remains a challenging research topic. Energy dissipation and efficiency have prevented the widespread use of FPGA devices in embedded systems. Helping overcome these challenges, this book offers solutions for the development of energy efficient applications using FPGAs. It provides a framework for high-level hardware-software application development, describes energy performance modeling for reconfigurable system-on-chip devices, and explores energy efficient designs for various applications. The authors present a two-step rapid energy estimation technique that enables high-level design space exploration and offer a hardware-software design for energy efficient implementations of operating systems.
List of Tables
List of Figures
Acknowledgments
Preface
Introduction
1(8)
Overview
1(2)
Challenges and Contributions
3(4)
Manuscript Organization
7(2)
Reconfigurable Hardware
9(40)
Reconfigurable System-on-Chips (SoCs)
9(20)
Field-Programmable Gate Arrays
9(7)
Pre-Compiled Embedded Hardware Components
16(4)
Soft Processors
20(7)
Domain-Specific Platform FPGAs
27(2)
Design Flows
29(20)
Low-Level Design Flows
30(1)
High-Level Design Flows
31(3)
System Generator for DSP
34(15)
A High-Level Hardware-Software Application Development Framework
49(28)
Introduction
49(2)
Related Work
51(3)
Our Approach
54(3)
An Implementation Based on Matlab/Simulink
57(7)
High-Level Design Description
58(1)
Arithmetic-Level Co-Simulation
58(5)
Rapid Hardware Resource Estimation
63(1)
Illustrative Examples
64(11)
Co-Simulation of the Processor and Hardware Peripherals
65(5)
Co-Simulation of a Complete Multi-Processor Platform
70(5)
Summary
75(2)
Energy Performance Modeling and Energy Efficient Mapping for a Class of Applications
77(22)
Introduction
77(2)
Knobs for Energy-Efficient Designs
79(1)
Related Work
80(1)
Performance Modeling of RSoC Architectures
81(4)
RSoC Model
82(2)
A Performance Model for Virtex-II Pro
84(1)
Problem Formulation
85(2)
Application Model
85(1)
Problem Definition
86(1)
Algorithm for Energy Minimization
87(2)
Trellis Creation
87(1)
A Dynamic Programming Algorithm
87(2)
Illustrative Examples
89(9)
Delay-and-Sum Beamforming
89(5)
Mvdr Beamforming
94(4)
Summary
98(1)
High-Level Rapid Energy Estimation and Design Space Exploration
99(54)
Introduction
99(3)
Related Work
102(2)
Energy Estimation Techniques
102(1)
High-Level Design Space Exploration
103(1)
Domain-Specific Modeling
104(13)
Domain-Specific Models for Matrix Multiplication
106(5)
High-Level Energy, Area, and Latency Functions
111(1)
Tradeoffs among Energy, Area, and Latency
112(5)
A Two-Step Rapid Energy Estimation Technique
117(9)
Step 1: Cycle-Accurate Arithmetic Level Co-Simulation
119(3)
Step 2: Energy Estimation
122(4)
Energy Estimation for Customized Hardware Components
126(10)
Software Architecture
126(3)
Overall Design Flow
129(1)
Kernel Level Development
130(4)
Application Level Development
134(2)
Instruction-Level Energy Estimation for Software Programs
136(10)
Arithmetic-Level Instruction Based Energy Estimation
136(2)
An Implementation
138(3)
Illustrative Examples
141(5)
Illustrative Examples
146(5)
Summary
151(2)
Hardware-Software Co-Design for Energy Efficient Implementations of Operating Systems
153(32)
Introduction
153(3)
Real-Time Operating Systems
156(3)
Background
156(1)
Off-the-Shelf Operating Systems
157(2)
On-Chip Energy Management Mechanisms
159(1)
Related Work
160(1)
Our Approach
161(2)
An Implementation Based on MicroC/OS-II
163(13)
Customization of MicroBlaze Soft Processor
163(2)
Clock Management Unit
165(1)
Auxiliary Task and Interrupt Management Unit
165(3)
Selective Wake-up and Activation State Management Unit
168(1)
Analysis of Management Overhead
169(2)
Illustrative Application Development
171(5)
An Implementation Based on TinyOS
176(7)
Hardware Architecture
177(2)
Illustrative Application Development
179(3)
Analysis of Management Overhead
182(1)
Summary
183(2)
Concluding Remarks and Future Directions
185(2)
Concluding Remarks
185(1)
Future Work
185(2)
References 187(10)
Index 197
Jingzhao Ou works for the DSP Design Tools and Methodologies Group at Xilinx in San Jose, California.

Viktor K. Prasanna is the Charles Lee Powell Chair in Engineering and professor of electrical engineering and computer science at the University of Southern California.
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