Preface |
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xi | |
Acknowledgments |
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xiii | |
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1 | (8) |
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1.1 Adding Project-Specific Functions, Drive Strengths, Views, and Corners |
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4 | (1) |
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5 | (4) |
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9 | (30) |
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2.1 Lesson from the Real World: Manager's Perspective and Engineer's Perspective |
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9 | (2) |
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11 | (21) |
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2.2.1 Combinational Functions |
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12 | (14) |
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2.2.2 Sequential Functions |
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26 | (3) |
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29 | (3) |
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2.3 Extended Library Offerings |
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32 | (4) |
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32 | (4) |
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2.4 Boutique Library Offerings |
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36 | (1) |
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2.5 Concepts for Further Study |
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37 | (2) |
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39 | (13) |
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3.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective |
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39 | (1) |
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3.2 Extension Capable Architectures versus Function Complete Architectures |
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40 | (3) |
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3.3 Electrostatic Discharge Considerations |
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43 | (7) |
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45 | (1) |
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3.3.2 Custom Design Versus Standard IO Design Comparison |
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45 | (2) |
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3.3.3 The Need for Maintaining Multiple IO Footprint Regions on an IC |
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47 | (2) |
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49 | (1) |
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3.4 Concepts for Further Study |
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50 | (2) |
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52 | (11) |
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4.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective |
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52 | (3) |
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4.2 Single Ports, Dual Ports, and ROM: The Compiler |
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55 | (3) |
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4.3 Nonvolatile Memories: The Block |
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58 | (2) |
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4.4 Special-Purpose Memories: The Custom |
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60 | (2) |
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4.5 Concepts for Further Study |
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62 | (1) |
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63 | (17) |
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5.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective |
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63 | (3) |
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5.2 Phase-Locked Loops, Power-On Resets, and Other Small-Scale Integration Analogs |
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66 | (3) |
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5.3 Low-Power Support Structures |
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69 | (2) |
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71 | (4) |
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72 | (1) |
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72 | (1) |
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73 | (1) |
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73 | (1) |
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74 | (1) |
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74 | (1) |
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75 | (1) |
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75 | (1) |
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75 | (1) |
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5.5 Hard, Firm, and Soft Boxes |
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75 | (3) |
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5.6 Concepts for Further Study |
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78 | (2) |
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80 | (15) |
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6.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective |
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80 | (2) |
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6.2 Picking an Architecture |
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82 | (4) |
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86 | (3) |
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6.4 The Need and the Way to Work with Fabrication Houses |
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89 | (3) |
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6.5 Concepts for Further Study |
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92 | (3) |
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95 | (14) |
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7.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective |
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95 | (4) |
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7.2 Why a Tool More Than 40 Years Old Is Still Useful |
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99 | (3) |
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7.3 Accuracy, Reality, and Why SPICE Results Must be Viewed with a Wary Eye |
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102 | (4) |
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7.4 Sufficient Parasitics |
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106 | (1) |
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7.5 Concepts for Further Study |
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107 | (2) |
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109 | (36) |
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8.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective |
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109 | (1) |
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8.2 Performance Limits and Measurement |
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110 | (1) |
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8.3 Default Versus Conditional Arcs |
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110 | (2) |
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8.4 Break-Point Optimization |
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112 | (3) |
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8.5 A Word on Setup and Hold |
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115 | (7) |
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8.6 Failure Mechanisms and Roll-Off |
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122 | (2) |
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8.7 Supporting Efficient Synthesis |
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124 | (7) |
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8.7.1 SPICE, Monotonic Arrays, and Favorite Stdcells |
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124 | (5) |
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8.7.2 SPICE, Positive Arrays, and Useful Skew |
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129 | (2) |
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8.8 Supporting Efficient Timing Closure |
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131 | (3) |
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8.9 Design Corner Specific Timing Views |
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134 | (6) |
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8.10 Nonlinear Timing Views are so "Old Hat"... |
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140 | (2) |
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8.11 Concepts for Further Study |
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142 | (3) |
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145 | (15) |
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9.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective |
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145 | (2) |
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9.2 Timing Arcs Versus Power Arcs |
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147 | (1) |
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148 | (2) |
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9.4 Real Versus Measured Dynamic Power |
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150 | (3) |
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9.5 Should Power Be Built as a Monotonic Array? |
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153 | (2) |
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9.6 Best-Case and Worst-case Power Views Versus Best-Case and Worst-Case Timing Views |
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155 | (1) |
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9.7 Efficiently Measuring Power |
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156 | (2) |
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9.8 Concepts for Further Study |
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158 | (2) |
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160 | (10) |
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10.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective |
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160 | (2) |
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10.2 Noise Arcs Versus Timing and Power Arcs |
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162 | (3) |
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165 | (1) |
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10.4 The Not-So-Easy Part |
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166 | (2) |
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10.5 Concepts for Further Study |
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168 | (2) |
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170 | (11) |
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11.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective |
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170 | (1) |
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11.2 Consistency Across Simulators |
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171 | (6) |
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175 | (2) |
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11.3 Consistency with Timing, Power & Noise Views |
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177 | (3) |
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11.4 Concepts for Further Study |
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180 | (1) |
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181 | (12) |
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12.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective |
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181 | (3) |
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12.2 Supporting Reachability |
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184 | (5) |
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12.3 Supporting Observability |
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189 | (2) |
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12.4 Concepts for Further Study |
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191 | (2) |
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193 | (16) |
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13.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective |
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193 | (2) |
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13.2 Validating Views across a Library |
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195 | (4) |
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13.3 Validating Stdcells Across a Technology Node |
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199 | (5) |
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13.4 Validating Libraries Across Multiple Technology Nodes |
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204 | (4) |
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13.5 Concepts for Further Study |
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208 | (1) |
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14 Design for Manufacturability |
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209 | (17) |
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14.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective |
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209 | (2) |
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211 | (13) |
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14.2.1 Design for Manufacturability or Design for Mediocrity? |
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211 | (4) |
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14.2.2 Design for Methodology and Design for Mobility (Between Fabrication Houses)? |
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215 | (2) |
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14.2.3 Design for Models and Design for Measurement |
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217 | (2) |
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14.2.4 Design for Management and Design for Metrics |
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219 | (2) |
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221 | (2) |
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223 | (1) |
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14.3 Concepts for Further Study |
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224 | (2) |
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226 | (11) |
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15.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective |
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226 | (3) |
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229 | (7) |
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15.2.1 Tin: Engineering Work in Progress |
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229 | (1) |
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15.2.2 Silver: Expert Use Only |
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230 | (2) |
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15.2.3 Gold: Ready for General Use |
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232 | (3) |
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15.2.4 Platinum: Long-Standing and Stable |
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235 | (1) |
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15.3 Concepts for Further Study |
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236 | (1) |
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16 Playing with the Physical Design Kit: Usually "At Your Own Risk" |
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237 | (10) |
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16.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective |
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237 | (3) |
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240 | (3) |
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16.3 Added Unsupported Devices |
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243 | (2) |
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16.4 Concepts for Further Study |
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245 | (2) |
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17 Tagging and Revisioning |
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247 | (13) |
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17.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective |
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247 | (1) |
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17.2 Tagging and Time Stamps |
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248 | (6) |
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248 | (3) |
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251 | (3) |
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17.3 Metadata, Directory Structures, and Pointers |
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254 | (4) |
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17.4 Concepts for Further Study |
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258 | (2) |
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18 Releasing and Supporting |
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260 | (16) |
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18.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective |
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260 | (3) |
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18.2 When Is Test Silicon Needed for Verification? |
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263 | (2) |
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18.3 Sending the Baby Out the Door |
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265 | (4) |
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18.3.1 Validation Reports |
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265 | (2) |
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18.3.2 Verification Reports |
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267 | (2) |
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18.4 Multiple Quality Levels on the Same Design |
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269 | (2) |
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18.5 Supporting "Bug Fixes" |
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271 | (3) |
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18.6 Concepts for Further Study |
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274 | (2) |
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276 | (19) |
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19.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective |
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276 | (3) |
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19.2 Supporting High-Speed Design |
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279 | (4) |
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19.3 Supporting Low-Power Design |
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283 | (3) |
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19.4 Supporting Third-Party Libraries |
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286 | (3) |
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19.5 Supporting Black Box Third-Party IP (Intellectual Property) Design |
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289 | (3) |
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19.6 Supporting Multiple Library Design |
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292 | (1) |
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19.7 Concepts for Further Study |
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293 | (2) |
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295 | (10) |
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20.1 Manager's Perspective |
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295 | (3) |
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20.2 Customer's Perspective |
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298 | (2) |
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20.3 Vendor's Perspective |
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300 | (1) |
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20.4 Engineer's Perspective |
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301 | (1) |
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20.5 Concepts for Further Study |
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302 | (1) |
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302 | (3) |
Appendix I Minimum Library Synthesis Versus Full-Library Synthesis of a Four-Bit Flash Adder |
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305 | (6) |
Appendix II Pertinent CMOS BSIM Spice Parameters with Units and Default Levels |
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311 | (2) |
Appendix III Definition of Terms |
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313 | (4) |
Appendix IV One Possible Means of Formalized Monthly Reporting |
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317 | (2) |
Index |
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319 | |