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E-raamat: Engineering the CMOS Library: Enhancing Digital Design Kits for Competitive Silicon

  • Formaat: PDF+DRM
  • Ilmumisaeg: 16-Feb-2012
  • Kirjastus: John Wiley & Sons Inc
  • Keel: eng
  • ISBN-13: 9781118273111
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  • Formaat: PDF+DRM
  • Ilmumisaeg: 16-Feb-2012
  • Kirjastus: John Wiley & Sons Inc
  • Keel: eng
  • ISBN-13: 9781118273111
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"This book is about gaining a competitive edge in the Integrated Circuit IC marketplace"--

"This book is about gaining a competitive edge in the Integrated Circuit IC marketplace. It suggests that there is an unrecognized value hidden in the safety margins of descriptive views in any piece of intellectual property (IP). This hidden value is normally left on the table. However, it can be used by the aggressive design engineer (or manager) to surpass the competition in the marketplace. This text reveals how the typical design house can enhance performance, reduce power, and improve the density of standard-cell logic. It will show how to add value to the generic, foundry-provided standard-cell library that most companies use without modification. Lastly, it identifies the low-risk opportunities aggressive designers and managers can employ to improve margin from overdesigned standard cells. "--



Shows readers how to gain the competitive edge in the integrated circuit marketplace

This book offers a wholly unique perspective on the digital design kit. It points to hidden value in the safety margins of standard-cell libraries and shows design engineers and managers how to use this knowledge to beat the competition.

Engineering the CMOS Library reveals step by step how the generic, foundry-provided standard-cell library is built, and how to extract value from existing std-cells and EDA tools in order to produce tighter-margined, smaller, faster, less power-hungry, and more yield-producing integrated circuits. It explores all aspects of the digital design kit, including the different views of CMOS std-cell libraries along with coverage of IO libraries, memory compilers, and small analog blocks. Readers will learn:

  • How to work with overdesigned std-cell libraries to improve profitability while maintaining safety

  • How functions usually found in std-cell libraries cover the design environment, and how to add any missing functions

  • How to harness the characterization technique used by vendors to add characterization without having to get it from the vendor

  • How to use verification and validation techniques to ensure proper descriptive views and even fix inconsistencies in vendor release views

  • How to correct for possible conflicts arising from multiple versions and different vendor sources in any given integrated circuit design

Complete with real-world case studies, examples, and suggestions for further research, Engineering the CMOS Library will help readers become more astute designers.

Preface xi
Acknowledgments xiii
1 Introduction
1(8)
1.1 Adding Project-Specific Functions, Drive Strengths, Views, and Corners
4(1)
1.2 What Is a DDK?
5(4)
2 Stdcell Libraries
9(30)
2.1 Lesson from the Real World: Manager's Perspective and Engineer's Perspective
9(2)
2.2 What Is a Stdcell?
11(21)
2.2.1 Combinational Functions
12(14)
2.2.2 Sequential Functions
26(3)
2.2.3 Clock Functions
29(3)
2.3 Extended Library Offerings
32(4)
2.3.1 Low-Power Support
32(4)
2.4 Boutique Library Offerings
36(1)
2.5 Concepts for Further Study
37(2)
3 IO Libraries
39(13)
3.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective
39(1)
3.2 Extension Capable Architectures versus Function Complete Architectures
40(3)
3.3 Electrostatic Discharge Considerations
43(7)
3.3.1 Footprints
45(1)
3.3.2 Custom Design Versus Standard IO Design Comparison
45(2)
3.3.3 The Need for Maintaining Multiple IO Footprint Regions on an IC
47(2)
3.3.4 Circuit Under Pad
49(1)
3.4 Concepts for Further Study
50(2)
4 Memory Compilers
52(11)
4.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective
52(3)
4.2 Single Ports, Dual Ports, and ROM: The Compiler
55(3)
4.3 Nonvolatile Memories: The Block
58(2)
4.4 Special-Purpose Memories: The Custom
60(2)
4.5 Concepts for Further Study
62(1)
5 Other Functions
63(17)
5.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective
63(3)
5.2 Phase-Locked Loops, Power-On Resets, and Other Small-Scale Integration Analogs
66(3)
5.3 Low-Power Support Structures
69(2)
5.4 Stitching Structures
71(4)
5.4.1 Core-Fill Cells
72(1)
5.4.2 IO-Fill Cells
72(1)
5.4.3 DECAP Cells
73(1)
5.4.4 CMP-Fill Cells
73(1)
5.4.5 Spare Logic Cells
74(1)
5.4.6 Probe-Point Cells
74(1)
5.4.7 Antenna Diodes
75(1)
5.4.8 Test-Debug Diodes
75(1)
5.4.9 Others
75(1)
5.5 Hard, Firm, and Soft Boxes
75(3)
5.6 Concepts for Further Study
78(2)
6 Physical Views
80(15)
6.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective
80(2)
6.2 Picking an Architecture
82(4)
6.3 Measuring Density
86(3)
6.4 The Need and the Way to Work with Fabrication Houses
89(3)
6.5 Concepts for Further Study
92(3)
7 Spice
95(14)
7.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective
95(4)
7.2 Why a Tool More Than 40 Years Old Is Still Useful
99(3)
7.3 Accuracy, Reality, and Why SPICE Results Must be Viewed with a Wary Eye
102(4)
7.4 Sufficient Parasitics
106(1)
7.5 Concepts for Further Study
107(2)
8 Timing Views
109(36)
8.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective
109(1)
8.2 Performance Limits and Measurement
110(1)
8.3 Default Versus Conditional Arcs
110(2)
8.4 Break-Point Optimization
112(3)
8.5 A Word on Setup and Hold
115(7)
8.6 Failure Mechanisms and Roll-Off
122(2)
8.7 Supporting Efficient Synthesis
124(7)
8.7.1 SPICE, Monotonic Arrays, and Favorite Stdcells
124(5)
8.7.2 SPICE, Positive Arrays, and Useful Skew
129(2)
8.8 Supporting Efficient Timing Closure
131(3)
8.9 Design Corner Specific Timing Views
134(6)
8.10 Nonlinear Timing Views are so "Old Hat"...
140(2)
8.11 Concepts for Further Study
142(3)
9 Power Views
145(15)
9.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective
145(2)
9.2 Timing Arcs Versus Power Arcs
147(1)
9.3 Static Power
148(2)
9.4 Real Versus Measured Dynamic Power
150(3)
9.5 Should Power Be Built as a Monotonic Array?
153(2)
9.6 Best-Case and Worst-case Power Views Versus Best-Case and Worst-Case Timing Views
155(1)
9.7 Efficiently Measuring Power
156(2)
9.8 Concepts for Further Study
158(2)
10 Noise Views
160(10)
10.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective
160(2)
10.2 Noise Arcs Versus Timing and Power Arcs
162(3)
10.3 The Easy Part
165(1)
10.4 The Not-So-Easy Part
166(2)
10.5 Concepts for Further Study
168(2)
11 Logical Views
170(11)
11.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective
170(1)
11.2 Consistency Across Simulators
171(6)
11.2.1 Efficient Testing
175(2)
11.3 Consistency with Timing, Power & Noise Views
177(3)
11.4 Concepts for Further Study
180(1)
12 Test Views
181(12)
12.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective
181(3)
12.2 Supporting Reachability
184(5)
12.3 Supporting Observability
189(2)
12.4 Concepts for Further Study
191(2)
13 Consistency
193(16)
13.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective
193(2)
13.2 Validating Views across a Library
195(4)
13.3 Validating Stdcells Across a Technology Node
199(5)
13.4 Validating Libraries Across Multiple Technology Nodes
204(4)
13.5 Concepts for Further Study
208(1)
14 Design for Manufacturability
209(17)
14.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective
209(2)
14.2 What is DFM?
211(13)
14.2.1 Design for Manufacturability or Design for Mediocrity?
211(4)
14.2.2 Design for Methodology and Design for Mobility (Between Fabrication Houses)?
215(2)
14.2.3 Design for Models and Design for Measurement
217(2)
14.2.4 Design for Management and Design for Metrics
219(2)
14.2.5 Design for Market
221(2)
14.2.6 Design for Money
223(1)
14.3 Concepts for Further Study
224(2)
15 Validation
226(11)
15.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective
226(3)
15.2 Quality Levels
229(7)
15.2.1 Tin: Engineering Work in Progress
229(1)
15.2.2 Silver: Expert Use Only
230(2)
15.2.3 Gold: Ready for General Use
232(3)
15.2.4 Platinum: Long-Standing and Stable
235(1)
15.3 Concepts for Further Study
236(1)
16 Playing with the Physical Design Kit: Usually "At Your Own Risk"
237(10)
16.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective
237(3)
16.2 Manipulating Models
240(3)
16.3 Added Unsupported Devices
243(2)
16.4 Concepts for Further Study
245(2)
17 Tagging and Revisioning
247(13)
17.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective
247(1)
17.2 Tagging and Time Stamps
248(6)
17.2.1 ASCII
248(3)
17.2.2 Binary
251(3)
17.3 Metadata, Directory Structures, and Pointers
254(4)
17.4 Concepts for Further Study
258(2)
18 Releasing and Supporting
260(16)
18.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective
260(3)
18.2 When Is Test Silicon Needed for Verification?
263(2)
18.3 Sending the Baby Out the Door
265(4)
18.3.1 Validation Reports
265(2)
18.3.2 Verification Reports
267(2)
18.4 Multiple Quality Levels on the Same Design
269(2)
18.5 Supporting "Bug Fixes"
271(3)
18.6 Concepts for Further Study
274(2)
19 Other Topics
276(19)
19.1 Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective
276(3)
19.2 Supporting High-Speed Design
279(4)
19.3 Supporting Low-Power Design
283(3)
19.4 Supporting Third-Party Libraries
286(3)
19.5 Supporting Black Box Third-Party IP (Intellectual Property) Design
289(3)
19.6 Supporting Multiple Library Design
292(1)
19.7 Concepts for Further Study
293(2)
20 Communications
295(10)
20.1 Manager's Perspective
295(3)
20.2 Customer's Perspective
298(2)
20.3 Vendor's Perspective
300(1)
20.4 Engineer's Perspective
301(1)
20.5 Concepts for Further Study
302(1)
20.6 Conclusions
302(3)
Appendix I Minimum Library Synthesis Versus Full-Library Synthesis of a Four-Bit Flash Adder 305(6)
Appendix II Pertinent CMOS BSIM Spice Parameters with Units and Default Levels 311(2)
Appendix III Definition of Terms 313(4)
Appendix IV One Possible Means of Formalized Monthly Reporting 317(2)
Index 319
David Doman is Circuit Manager at GlobalFoundries in Austin, Texas. He has more than thirty years of experience in semiconductor intellectual property design and development.