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E-raamat: ESD: Failure Mechanisms and Models

Steven H. Voldman (IEEE Fellow, Vermont, USA)

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Ilmumisaeg: 01-Jul-2009
Kirjastus: John Wiley & Sons Inc
Keel: eng
ISBN-13: 9780470747261

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Formaat: PDF+DRM
Ilmumisaeg: 01-Jul-2009
Kirjastus: John Wiley & Sons Inc
Keel: eng
ISBN-13: 9780470747261

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Circuits & components

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Electrostatic discharge (ESD) failure mechanisms continue to impact semiconductor components and systems as technologies scale from micro- to nano-electronics.

This book studies electrical overstress, ESD, and latchup from a failure analysis and case-study approach. It provides a clear insight into the physics of failure from a generalist perspective, followed by investigation of failure mechanisms in specific technologies, circuits, and systems. The book is unique in covering both the failure mechanism and the practical solutions to fix the problem from either a technology or circuit methodology.

Look inside for extensive coverage on:

failure analysis tools, EOS and ESD failure sources and failure models of semiconductor technology, and how to use failure analysis to design more robust semiconductor components and systems;
electro-thermal models and technologies; the state-of-the-art technologies discussed include CMOS, BiCMOS, silicon on insulator (SOI), bipolar technology, high voltage CMOS (HVCMOS), RF CMOS, smart power, gallium arsenide (GaAs), gallium nitride (GaN), magneto-resistive (MR) , giant magneto-resistors (GMR), tunneling magneto-resistor (TMR), devices; micro electro-mechanical (MEM) systems, and photo-masks and reticles;
practical methods to use failure analysis for the understanding of ESD circuit operation, temperature analysis, power distribution, ground rule development, internal bus distribution, current path analysis, quality metrics, (connecting the theoretical to the practical analysis);
the failure of each key element of a technology from passives, active elements to the circuit, sub-system to package, highlighted by case studies of the elements, circuits and system-on-chip (SOC) in today’s products.

ESD: Failure Mechanisms and Models is a continuation of the author’s series of books on ESD protection. It is an essential reference and a useful insight into the issues that confront modern technology as we enter the Nano-electronic era.

About the Author

xvii

Preface

xix

Acknowledgments

xxiii

Failure Analysis and ESD

(30)

Introduction

(15)

FA Techniques for Evaluation of ESD Events

(1)

Fundamental Concepts of ESD FA Methods and Practices

(1)

ESD Failure: Why Do Semiconductor Chips Fail?

(1)

How to Use FA to Design ESD Robust Technologies

(1)

How to Use FA to Design ESD Robust Circuits

(1)

How to Use FA for Temperature Prediction

(1)

How to Use Failure Models for Power Prediction

(1)

FA Methods, Design Rules, and ESD Ground Rules

(1)

FA and Semiconductor Process-Induced ESD Design Asymmetry

(1)

FA Methodology and Electro-thermal Simulation

(1)

FA and ESD Testing Methodology

(3)

FA Methodology for Evaluation of ESD Parasitics

(1)

FA Methods and ESD Device Operation Verification

(1)

FA Methodology to Evaluate Inter-power Rail Electrical Connectivity

(2)

How to Use FA to Eliminate Failure Mechanisms

(1)

ESD Failure: How Do Micro-electronic Devices Fail?

(4)

ESD Failure: How Do Metallurgical Junctions Fail?

(1)

ESD Failure: How Do Insulators Fail?

(1)

ESD Failure: How Do Metals Fail?

(1)

Sensitivity of Semiconductor Components

(4)

ESD Sensitivity as a Function of Materials

(1)

ESD Sensitivity as a Function of Semiconductor Devices

(1)

ESD Sensitivity as a Function of Product Type

(1)

ESD and Technology Scaling

(2)

ESD Technology Roadmap

(1)

How Do Semiconductor Chips Fail---Are the Failures Random or Systematic?

(2)

Closing Comments and Summary

(1)

Problems

(1)

References

(4)

Failure Analysis Tools, Models, and Physics of Failure

(46)

FA Techniques for Evaluation of ESD Events

(3)

FA Tools

(9)

Optical Microscope

(1)

Scanning Electron Microscope

(1)

Transmission Electron Microscope

(1)

Emission Microscope

(1)

Thermally Induced Voltage Alteration

(1)

Superconducting Quantum Interference Device Microscope

(1)

Atomic Force Microscope

(2)

The 2-D AFM

(1)

Picosecond Current Analysis Tool

(2)

Transmission Line Pulse---Picosecond Current Analysis Tool

(1)

ESD Simulation: ESD Pulse Models

(11)

Human Body Model

(1)

Machine Model

(1)

Cassette Model

(1)

Socketed Device Model

(1)

Charged Board Model

(1)

Cable Discharge Event

(2)

IEC System-Level Pulse Model

(1)

Human Metal Model

(1)

Transmission Line Pulse Testing

(2)

Very Fast Transmission Line Pulse (VF-TLP) Model

(1)

Ultra-fast Transmission Line Pulse (UF-TLP) Model

(1)

Electro-Thermal Physical Models

(14)

Tasca Model

(2)

Wunsch-Bell Model

(4)

Smith-Littau Model

(2)

Ash Model

(1)

Arkihpov, Astvatsaturyan, Godovosyn, and Rudenko Model

(1)

Dwyer, Franklin, and Campbell Model

(4)

Vlasov-Sinkevitch Model

(1)

Statistical Models for ESD Prediction

(2)

Closing Comments and Summary

(1)

Problems

(1)

References

(6)

CMOS Failure Mechanisms

(48)

Tables of CMOS ESD Failure Mechanisms

(1)

LOCOS Isolation-Defined CMOS

(9)

LOCOS-Bound Structures

(1)

LOCOS-Bound P+/N-well Junction Diode

(1)

LOCOS-Bound N+/P- Substrate Junction Diode

(1)

LOCOS-Bound N-Well/P- Substrate Junction Diode

(1)

LOCOS-Bound Lateral N-well to N-well

(1)

LOCOS-Bound Lateral N+ to N-well

(1)

LOCOS-Bound Lateral PNP Bipolar

(1)

LOCOS-Bound Thick Oxide MOSFET

(1)

Shallow Trench Isolation (STI)

(4)

STI Pull-down ESD Failure Mechanism

(1)

STI Pull-down and Gate Wrap-around

(1)

Silicides and Diodes

(1)

Non-silicide Diode Structures

(1)

STI-Defined P+/N-well Diode

(1)

STI-Defined N-well to Substrate Diode

(2)

STI Lateral N-well to N-well NPN Structures

(1)

Polysilicon-Defined Devices

(2)

Polysilicon-Bound Gated Diode

(1)

Lateral Diode with Block Mask

(1)

MOSFETs

(7)

N-channel MOSFETs

(2)

N-channel Multi-finger MOSFETs

(2)

Cascoded Series N-channel MOSFETs

(1)

P-channel MOSFETs

(1)

P-channel Multi-finger MOSFETs

(1)

Tungsten Silicide Gate MOSFET

(1)

Polysilicon Silicide Gate MOSFET

(1)

Metal Gate/High k Dielectric MOSFET

(1)

Resistors

(3)

Diffused Resistors

(1)

N-well Resistors

(2)

Buried Resistors

101

(1)

Silicide Blocked N-diffusion Resistors

102

(1)

Interconnects: Wires, Vias, and Contacts

102

(10)

Aluminum Interconnects

103

(1)

Copper Interconnects

104

(3)

Tungsten Interconnects

107

(1)

Vias

107

(3)

Contacts

110

(2)

ESD Failure in CMOS Nanostructures

112

(6)

ESD Failures in 130 nm Technology

112

(1)

ESD Failures in 90 nm Technology

113

(1)

ESD Failures in 65 nm Technology

114

(1)

ESD Failures in 45 nm Technology

115

(1)

ESD Failures in 32 nm Technology

115

(1)

ESD Failures in 22 nm Technology

116

(2)

Closing Comments and Summary

118

(1)

Problems

118

(1)

References

119

(6)

CMOS Circuits: Receivers and Off-Chip Drivers

125

(34)

Table of CMOS Receiver and OCD ESD Failure Mechanisms

125

(1)

Receiver Circuits

125

(2)

Receivers Circuits with ESD Networks

127

(4)

Receiver with Dual Diode and Series Resistor

127

(1)

Receiver with Diode-Resistor-Diode

128

(1)

Receiver with Diode-Resistor-MOSFET

128

(3)

Receiver Circuits with Half-Pass Transmission Gate

131

(3)

Receiver with Full-Pass Transmission Gate

134

(1)

Receiver with Full-Pass Transmission Gate with Second Power Source

135

(1)

Receiver, Half-Pass Transmission Gate, and Keeper Network

135

(4)

Receiver, Half-Pass Transmission Gate, and the Modified Keeper Network

138

(1)

Receiver Circuits with Pseudo-Zero VT Half-Pass Transmission Gate

139

(2)

Receiver with Zero VT Transmission Gate

141

(2)

Receiver Circuits with Bleed Transistors

143

(1)

Receiver Circuits with Test Functions

144

(2)

Receiver with Schmitt Trigger Feedback Networks

146

(2)

Off-Chip Drivers

148

(1)

OCD Design Process-Related ESD Failure

148

(1)

Single NFET Pull-down OCD

149

(1)

Series Cascode MOSFETs

150

(2)

I/O Design Considerations and ESD Parasitic Failure Mechanisms

152

(3)

Layout-Dependent ESD Failure Mechanisms

153

(2)

Closing Comments and Summary

155

(1)

Problems

155

(1)

References

156

(3)

CMOS Integration

159

(36)

Table of CMOS Integration ESD Failure Mechanisms

159

(1)

Architcture and Design Synthesis-Related Failures

159

(2)

Alternate Current Loop

161

(1)

Chip Capacitance

161

(1)

ESD Power Clamps

161

(1)

Intra- and Inter-domain ESD Protection

162

(1)

Split Ground Configurations

162

(1)

Mixed Voltage Interface

163

(5)

Peripheral Vcc and Core VDD Power Rails

163

(1)

Two Power Supply: Peripheral and Core VDD Power Rails

164

(2)

Voltage Regulators

166

(2)

Mixed Signal Interface

168

(2)

Digital and Analog

168

(1)

Digital, Analog, and RF

169

(1)

Inter-domain Signal Line ESD Failures

170

(3)

Digital-to-Analog Signal Line Failures

170

(3)

Decoupling Capacitors

173

(1)

System Clock and Phase-Locked Loop

174

(1)

Fuse Networks

174

(4)

Fuse Networks and ESD Failure Mechanisms

174

(2)

eFUSE and ESD Failure Mechanisms

176

(2)

Bond Pads

178

(3)

Floating Bond Pads

178

(1)

Floating Bond Pads over Interconnects

179

(1)

Bond Pad Failure: Programmable VDD

180

(1)

Bond Pad to Bond Pad ESD Failures

180

(1)

Bond Pad Failure: ESD Structures under Bond Pads

181

(1)

MOSFET Gate Structure

181

(1)

MOSFET Floating Gate and Floating Gate Tie Down

181

(1)

MOSFET Gates Connected to Power VDD

182

(1)

Fill Shapes

182

(1)

No Connects

182

(1)

Test Circuitry

183

(1)

Multi-chip Systems

183

(2)

Multi-chip systems on Multi-layer Ceramic

183

(1)

Multi-chip Systems and Silicon Carriers

184

(1)

Multi-chip Systems: Chip-to-Chip Failures with Adjacent Chips

184

(1)

Multi-chip Systems: Proximity Communications

185

(1)

CMOS Latchup Failures

185

(3)

Table of Latchup Failures

185

(2)

Latchup Failure Mechanisms

187

(1)

Closing Comments and Summary

188

(1)

Problems

189

(2)

References

191

(4)

SOI ESD Failure Mechanisms

195

(30)

Tables of SOI Device and Integration ESD Failure Mechanisms

195

(2)

SOI N-channel MOSFETs

197

(2)

SOI Single-Finger N-channel MOSFETs

197

(1)

SOI Multi-finger MOSFETs

198

(1)

SOI Diodes

199

(2)

SOI Poly-bound Gated Diode

199

(1)

SOI Poly-bound Gated Diode with Halo Implants

199

(2)

SOI Buried Resistors

201

(1)

SOI Failure Mechanisms in 150 nm Technology

202

(2)

Lateral Graded Gated SOI Diode Structure

203

(1)

Lateral Ungated SOI Diode Structure

203

(1)

SOI ESD Failure Mechanisms in 45 nm Technology

204

(2)

SOI Lateral Gated Diode

204

(1)

SOI Double-Well Field Effect Device

204

(1)

SOI: ESD under BOX

205

(1)

SOI ESD Failure Mechanisms in 32 nm Technology

206

(1)

SOI ESD Failure Mechanisms in 22 nm Technology and the Future

207

(3)

SOI Design Synthesis and ESD Failure Mechanisms

210

(7)

SOI ESD Circuit Failure Mechanisms

210

(2)

Mixed Voltage SOI ESD Circuit Failure Mechanisms

212

(2)

SOI Receiver Network ESD Failures

214

(1)

SOI Fuse Networks

215

(1)

SOI Dynamic Threshold Circuitry

215

(1)

SOI Active Clamp Circuitry

216

(1)

SOI Integration: ESD Failure Mechanisms

217

(1)

Closing Comments and Summary

218

(1)

Problems

218

(2)

References

220

(5)

RF COMS and ESD

225

(34)

Tables of RF CMOS ESD Failure Mechanisms

225

(3)

RF MOSFET

228

(1)

RF Shallow Trench Isolation Diode

229

(2)

RF Polysilicon Gated Diode

231

(1)

Silicon-Controlled Rectifier

232

(1)

Schottky Barrier Diodes

233

(2)

Capacitors

235

(6)

MIM Capacitor

236

(1)

Varactors and Hyper-abrupt Varactor Capacitors

237

(1)

Metal-ILD-Metal Capacitor

237

(1)

VPP Capacitor

237

(4)

Decoupling Capacitor

241

(1)

Resistors

241

(4)

Silicon Resistors

241

(1)

Polysilicon Resistors

241

(1)

Electronic Fuse (eFUSE) Resistor

241

(4)

Inductors

245

(5)

Planar Inductors

245

(3)

T-coil Inductor Pairs

248

(2)

Examples of RF ESD Circuit Failure Mechanisms

250

(3)

Closing Comments and Summary

253

(1)

Problems

253

(1)

References

254

(5)

Micro-electromechnical Systems

259

(28)

Table of MEM Failure Mechanisms

260

(1)

Electrostatically Actuated Devices

260

(3)

Micro-mechanical Engines

263

(2)

Torsional Ratcheting Actuator

265

(2)

Electromagnetic Micro-power Generators

267

(2)

MEM Inductors

269

(1)

Electrostatically Actuated Variable Capacitor

270

(1)

Micro-mechanical Switches

271

(1)

RF MEM Switch

271

(6)

Micro-mechanical Mirrors

277

(1)

Electrostatically Actuated Torsional Micro-mirrors

277

(4)

Closing Comments and Summary

281

(1)

Problems

281

(1)

References

282

(5)

Gallium Arsenide

287

(28)

Tables of GaAs-Based ESD Failure Mechanisms

287

(3)

GaAs Technology

290

(1)

GaAs Energy-to-failure and Power-to-failure

290

(3)

GaAs ESD Failures in Active and Passive Elements

293

(1)

GaAs HBT Devices

294

(3)

GaAs HBT Device ESD Results

295

(1)

GaAs HBT Diode Strings

296

(1)

GaAs HBT-Based Passive Elements

297

(1)

GaAs HBT Base-Collector Varactor

297

(1)

GaAs PHEMT Devices

298

(2)

GaAs PHEMT Low Noise Amplifiers

299

(1)

GaAs Power Amplifiers

300

(3)

GaAs PAs with Off-Chip Protection

303

(1)

InGaAs

303

(3)

InGaAs/AlGaAs PHEMT Devices

304

(1)

InGaAs/AlGaAs PHEMT ESD Failure

305

(1)

Gallium Nitride

306

(3)

GaN ESD Failure Mechanisms

307

(2)

InP and ESD

309

(1)

Closing Comments and Summary

309

(1)

Problems

309

(1)

References

310

(5)

Smart Power, LDMOS, and BCD Technology

315

(18)

Tables of LDMOS ESD Failure Mechanisms

315

(2)

LOCOS-Defined LDMOS Devices

317

(2)

STI-Defined LDMOS Devices

319

(1)

STI-Defined Isolated LDMOS Transistors

320

(1)

LDMOS Transistors: ESD Electrical Measurements

321

(1)

LDMOS-Based ESD Networks

322

(1)

LDMOS ESD Failure Mechanisms

323

(1)

LDMOS Transistor Design Enhancement

324

(1)

Latchup Events in LDMOS and BCD Technology

324

(2)

Closing Comments and Summary

326

(1)

Problems

327

(1)

References

328

(5)

Magnetic Recording

333

(28)

Tables of Magnetic Recording Failure Mechanisms

333

(1)

MR Heads

334

(9)

MR Head Structure

335

(1)

MR Head Electrical Model

336

(1)

MR Head ESD Failures

337

(3)

AMR Head Failure Mechanisms

340

(2)

ESD Protection of MR Head

342

(1)

Inductive Heads

343

(3)

Inductive Head Structure

343

(1)

Inductive Head Structure: Electrical Schematic

344

(1)

Inductive Head Structure: ESD Failures

345

(1)

GMR Heads

346

(3)

GMR Head Structure

346

(1)

GMR Head ESD Failures

347

(1)

GMR Head ESD Protection

347

(2)

TMR Heads

349

(2)

TMR Structure

349

(1)

TMR ESD Results

349

(2)

TMR ESD Failure Mechanisms

351

(1)

ESD Solutions

351

(3)

Inductive Head Shunt

351

(1)

MR Shunt

351

(1)

Parasitic Magnetic Shields

352

(1)

Suspension ESD Shunt

352

(1)

Integration of a Silicon Chip

353

(1)

Deposited Amorphous Silicon ESD Diodes

353

(1)

Silicon Substrates

353

(1)

Closing Comments and Summary

354

(1)

Problems

354

(1)

References

355

(6)

Photo-masks and Reticles: Failure Mechanisms

361

(18)

Table of Photo-masks Failure Mechanisms

361

(1)

Photo-mask Failure Mechanisms

361

(3)

Photo-mask Inspection Tools

364

(1)

Photo-mask ESD Characterization

365

(1)

Electrical Breakdown versus Gap Spacing

365

(2)

Electrical Breakdown in Air: The Townsend Model

367

(1)

Electrical Breakdown in Air: Toepler's Spark Law

367

(1)

Air Breakdown: The Paschen Breakdown Model

367

(1)

Paschen Curve versus Reticle Breakdown Plot

368

(1)

Electrical Model of Photo-mask Breakdown

369

(2)

ESD Latent Damage

371

(1)

ESD Damage for Single verus Multiple Events

372

(1)

ESD Damage to Anti-reflective Coating

373

(2)

ESD Solutions in Photo-masks

375

(1)

Closing Comments and Summary

375

(1)

Problems

375

(1)

References

376

(3)

Index

379

Dr Steven H. Voldman received his B.S. in Engineering Science from the University of Buffalo (1979); M.S. EE (1981) and Electrical Engineer Degree (1982) from M.I.T; MS Engineering Physics (1986) and Ph.D EE (1991) from the University of Vermont under IBM's Resident Study Fellow Program. At M.I.T, he worked as a member of the M.I.T. Plasma Fusion Center, and the High Voltage Research Laboratory (HVRL). At IBM, as a reliability device engineer, his work include pioneering work in bipolar/ CMOS SRAM alpha particle and cosmic ray SER simulation, MOSFET gate-induced drain leakage (GIDL) mechanism, hot electron, epitaxy/well design, CMOS latchup, and ESD. Since 1986, he has been responsible for defining the IBM ESD/latchup strategy for CMOS, SOI, BiCMOS and RF CMOS and SiGe technologies. He has authored ESD and latchup publications in the area of MOSFET Scaling, device simulations, copper, low-k, MR heads, CMOS, SOI , Sage and SiGeC technology. Voldman served as SEMATECH ESD Working Group Chairman (1996-2000), ESD Association General Chairman and Board of Directors, International Reliability Physics (IRPS) ESD/Latchup Chairman, International Physical and Failure Analysis (IPFA) Symposium ESD Sub-Committee Chairman, ESD Association Standard Development Chairman on Transmission Line Pulse Testing, ESD Education Committee, and serves on the ISQED Committee, Taiwan ED Conference (T-ESDC) Technical Program Committee. Voldman has provided ESD lectures for universities (e.g. MIT Lecture Series, Taiwan National Chiao-Tung University, and Singapore Nanyang Technical University). He is a recipient of over 125 US patents, over 100 publications, and also provides talks on patenting, and invention. He has been featured in EE Times, Intellectual Property Law and Business and authored the first article on ESD phenomena for the October 2002 edition of Scientific American entitled Lightening Rods for Nanostructures, and Pour La Science, Le Scienze, and Swiat Nauk international editions. Dr. Voldman was recently accepted as the first IEEE Fellow for ESD phenomena in semiconductors for ' contributions to electrostatic discharge protection CMOS, SOI and SiGe technologies'.

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