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E-raamat: ESD Testing: From Components to Systems

(IEEE Fellow, Vermont, USA)
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  • Ilmumisaeg: 14-Oct-2016
  • Kirjastus: John Wiley & Sons Inc
  • Keel: eng
  • ISBN-13: 9781118707159
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ESD Testing: From Components to SystemsSuurem pilt
  • Formaat: EPUB+DRM
  • Ilmumisaeg: 14-Oct-2016
  • Kirjastus: John Wiley & Sons Inc
  • Keel: eng
  • ISBN-13: 9781118707159
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Presenting information on electrostatic discharge (ESD) and the characterization of semiconductor devices, this book examines ESD physical models and discusses the test systems and testing and specifications of each model, including the RF ESD test systems and magnetic recording (MR) systems and latchup.

With the evolution of semiconductor technology and global diversification of the semiconductor business, testing of semiconductor devices to systems for electrostatic discharge (ESD) and electrical overstress (EOS) has increased in importance.

ESD Testing: From Components to Systems updates the reader in the new tests, test models, and techniques in the characterization of semiconductor components for ESD, EOS, and latchup. 

Key features:

  • Provides understanding and knowledge of ESD models and specifications including human body model (HBM), machine model (MM), charged device model (CDM), charged board model (CBM), cable discharge events (CDE), human metal model (HMM), IEC 61000-4-2 and IEC 61000-4-5.
  • Discusses new testing methodologies such as transmission line pulse (TLP), to very fast transmission line pulse (VF-TLP), and future methods of long pulse TLP, to ultra-fast TLP (UF-TLP).
  • Describes both conventional testing and new testing techniques for both chip and system level evaluation.
  • Addresses EOS testing, electromagnetic compatibility (EMC) scanning, to current reconstruction methods.
  • Discusses latchup characterization and testing methodologies for evaluation of semiconductor technology to product testing. 

ESD Testing: From Components to Systems is part of the authors’ series of books on electrostatic discharge (ESD) protection; this book will be an invaluable reference for the professional semiconductor chip and system-level ESD and EOS test engineer. Semiconductor device and process development, circuit designers, quality, reliability and failure analysis engineers will also find it an essential reference.  In addition, its academic treatment will appeal to both senior and graduate students with interests in semiconductor process, device physics, semiconductor testing and experimental work.

About the Author xvii
Preface xix
Acknowledgments xxiii
1 Introduction 1(16)
1.1 Testing for ESD, EMI, EOS, EMC, and Latchup
1(1)
1.2 Component and System Level Testing
1(1)
1.3 Qualification Testing
2(1)
1.4 ESD Standards
3(3)
1.4.1 Standard Development-Standard Practice (SP) and Standard Test Methods (STMs)
3(1)
1.4.2 Repeatability
4(1)
1.4.3 Reproducibility
4(1)
1.4.4 Round Robin Testing
4(1)
1.4.5 Round Robin Statistical Analysis-k-Statistics
5(1)
1.4.6 Round Robin Statistical Analysis-h-Statistics
6(1)
1.5 Component Level Standards
6(1)
1.6 System Level Standards
7(1)
1.7 Factory and Material Standards
7(1)
1.8 Characterization Testing
8(4)
1.8.1 Semiconductor Component Level Characterization
9(1)
1.8.2 Semiconductor Device Level Characterization
9(1)
1.8.3 Wafer Level ESD Characterization Testing
9(1)
1.8.4 Device Characterization Tests on Circuits
10(1)
1.8.5 Device Characterization Tests on Components
10(1)
1.8.6 System level Characterization on Components
11(1)
1.8.7 Testing to Standard Specification Levels
11(1)
1.8.8 Testing to Failure
11(1)
1.9 ESD Library Characterization and Qualification
12(1)
1.10 ESD Component Standards and Chip Architectures
12(1)
1.10.1 Relationship Between ESD Standard Pin Combinations and Failure Mechanisms
12(1)
1.10.2 Relationship Between ESD Standard Pin Combinations and Chip Architecture
13(1)
1.11 System Level Characterization
13(1)
1.12 Summary and Closing Comments
13(1)
Problems
14(1)
References
15(2)
2 Human Body Model 17(26)
2.1 History
17(1)
2.2 Scope
18(1)
2.3 Purpose
18(1)
2.4 Pulse Waveform
18(1)
2.5 Equivalent Circuit
19(1)
2.6 Test Equipment
20(3)
2.7 Test Sequence and Procedure
23(2)
2.8 Failure Mechanisms
25(1)
2.9 HBM ESD Current Paths
26(2)
2.10 HBM ESD Protection Circuit Solutions
28(4)
2.11 Alternate Test Methods
32(2)
2.11.1 HBM Split Fixture Testing
32(1)
2.11.2 HBM Sample Testing
33(1)
2.11.3 HBM Wafer Level ESD Testing
33(1)
2.11.4 HBM Test Extraction Across the Device Under Test (DUT)
33(1)
2.12 HBM Two-Pin Stress
34(3)
2.12.1 HBM Two-Pin Stress-Advantages
37(1)
2.12.2 HBM Two-Pin Stress-Pin Combinations
37(1)
2.13 HBM Small Step Stress
37(1)
2.13.1 HBM Small Step Stress-Advantages
38(1)
2.13.2 HBM Small Step Stress-Data Analysis Methods
38(1)
2.13.3 HBM Small Step Stress-Design Optimization
38(1)
2.14 Summary and Closing Comments
38(1)
Problems
39(1)
References
39(4)
3 Machine Model 43(18)
3.1 History
43(1)
3.2 Scope
43(1)
3.3 Purpose
43(1)
3.4 Pulse Waveform
44(1)
3.4.1 Comparison of Machine Model (MM) and Human Body Model (HBM) Pulse Waveform
44(1)
3.5 Equivalent Circuit
45(1)
3.6 Test Equipment
45(2)
3.7 Test Sequence and Procedure
47(2)
3.8 Failure Mechanisms
49(1)
3.9 MM ESD Current Paths
49(3)
3.10 MM ESD Protection Circuit Solutions
52(3)
3.11 Alternate Test Methods
55(2)
3.11.1 Small Charge Model (SCM)
55(2)
3.12 Machine Model to Human Body Model Ratio
57(1)
3.13 Machine Model Status as an ESD Standard
58(1)
3.14 Summary and Closing Comments
58(1)
Problems
59(1)
References
59(2)
4 Charged Device Model (CDM) 61(23)
4.1 History
61(1)
4.2 Scope
61(1)
4.3 Purpose
62(1)
4.4 Pulse Waveform
62(3)
4.4.1 Charged Device Model Pulse Waveform
62(1)
4.4.2 Comparison of Charged Device Model (CDM) and Human Body Model (HBM) Pulse Waveform
63(2)
4.5 Equivalent Circuit
65(1)
4.6 Test Equipment
65(2)
4.7 Test Sequence and Procedure
67(2)
4.8 Failure Mechanisms
69(1)
4.9 CDM ESD Current Paths
70(2)
4.10 CDM ESD Protection Circuit Solutions
72(2)
4.11 Alternative Test Methods
74(1)
4.11.1 Alternative Test Methods — Socketed Device Model (SDM)
74(1)
4.12 Charged Board Model (CBM)
75(2)
4.12.1 Comparison of Charged Board Model (CBM) and Charged Device Model (CDM) Pulse Waveform
75(2)
4.12.2 Charged Board Model (CBM) as an ESD Standard
77(1)
4.13 Summary and Closing Comments
77(2)
Problems
79(1)
References
80(4)
5 Transmission Line Pulse (TLP) Testing 84(24)
5.1 History
84(1)
5.2 Scope
85(1)
5.3 Purpose
85(1)
5.4 Pulse Waveform
86(1)
5.5 Equivalent Circuit
87(1)
5.6 Test Equipment
88(7)
5.6.1 Current Source
90(1)
5.6.2 Time Domain Reflection (TDR)
90(1)
5.6.3 Time Domain Transmission (TDT)
91(1)
5.6.4 Time Domain Reflection and Transmission (TDRT)
91(1)
5.6.5 Commercial Transmission Line Pulse (TLP) Systems
92(3)
5.7 Test Sequence and Procedure
95(3)
5.7.1 TLP Pulse Analysis
96(1)
5.7.2 Measurement Window
96(1)
5.7.3 Measurement Analysis-TDR Voltage Waveform
96(1)
5.7.4 Measurement Analysis-Time Domain Reflection (TDR) Current Waveform
97(1)
5.7.5 Measurement Analysis-Time Domain Reflection (TDR) Current—Voltage Characteristic
98(1)
5.8 TLP Pulsed I-V Characteristic
98(3)
5.8.1 TLP I-V Characteristic Key Parameters
99(1)
5.8.2 TLP Power Versus Time
99(1)
5.8.3 TLP Power Versus Time-Measurement Analysis
100(1)
5.8.4 TLP Power-to-Failure Versus Pulse Width Plot
100(1)
5.9 Alternate Methods
101(3)
5.9.1 Long Duration TLP (LD-TLP)
101(1)
5.9.2 Long Duration TLP Time Domain
102(2)
5.10 TLP-to-HBM Ratio
104(1)
5.10.1 Comparison of Transmission Line Pulse (TLP) and Human Body Model (HBM) Pulse Width
104(1)
5.11 Summary and Closing Comments
104(1)
Problems
104(1)
References
105(3)
6 Very Fast Transmission Line Pulse (VF-TLP) Testing 108(22)
6.1 History
108(1)
6.2 Scope
108(1)
6.3 Purpose
108(1)
6.4 Pulse Waveform
109(2)
6.4.1 Comparison of VF-TLP Versus TLP Waveform
110(1)
6.5 Equivalent Circuit
111(1)
6.6 Test Equipment Configuration
111(6)
6.6.1 Current Source
112(1)
6.6.2 Time Domain Reflection (TDR)
112(1)
6.6.3 Time Domain Transmission (TDT)
112(1)
6.6.4 Time Domain Reflection and Transmission (TDRT)
113(1)
6.6.5 Early VF-TLP Systems
114(2)
6.6.6 Commercial VF-TLP Test Systems
116(1)
6.7 Test Sequence and Procedure
117(4)
6.7.1 VF-TLP Pulse Analysis
118(1)
6.7.2 Measurement Window
118(1)
6.7.3 Measurement Analysis-VF-TLP Voltage Waveform
118(1)
6.7.4 Measurement Analysis-Time Domain Reflectometry (TDR) Current Waveform
118(1)
6.7.5 Measurement Analysis-Time Domain Transmission (TDR) Current—Voltage Characteristics
119(2)
6.8 VF-TLP Pulsed I—V Characteristics
121(3)
6.8.1 VF-TLP Pulsed I—V Characteristic Key Parameters
121(1)
6.8.2 VF-TLP Power Versus Time Plot
122(1)
6.8.3 VF-TLP Power Versus Time — Measurement Analysis
123(1)
6.8.4 VF-TLP Power-to-Failure Versus Pulse Width Plot
123(1)
6.8.5 VF-TLP and TLP Power-to-Failure Plot
124(1)
6.9 Alternate Test Methods
124(1)
6.9.1 Radio Frequency (RF) VF-TLP Systems
124(1)
6.9.2 Ultrafast Transmission Line Pulse (UF-TLP)
125(1)
6.10 Summary and Closing Comments
125(3)
Problems
128(1)
References
128(2)
7 IEC 61000-4-2 130(17)
7.1 History
130(1)
7.2 Scope
130(1)
7.3 Purpose
130(1)
7.3.1 Air Discharge
131(1)
7.3.2 Direct Contact Discharge
131(1)
7.4 Pulse Waveform
131(2)
7.4.1 Pulse Waveform Equation
132(1)
7.5 Equivalent Circuit
133(1)
7.6 Test Equipment
133(2)
7.6.1 Test Configuration
134(1)
7.6.2 ESD Guns
134(1)
7.6.3 ESD Guns - Standard Versus Discharge Module
135(1)
7.6.4 Human Body Model Versus IEC 61000-4-2
135(1)
7.7 Test Sequence and Procedure
135(2)
7.8 Failure Mechanisms
137(1)
7.9 IEC 61000-4-2 ESD Current Paths
138(1)
7.10 ESD Protection Circuitry Solutions
139(1)
7.11 Alternative Test Methods
140(3)
7.11.1 Automotive ESD Standards
141(1)
7.11.2 Medical ESD Standards
142(1)
7.11.3 Avionic ESD Standard
143(1)
7.11.4 Military-Related ESD Standard
143(1)
7.12 Summary and Closing Comments
143(1)
Problems
143(1)
References
144(3)
8 Human Metal Model (HMM) 147(16)
8.1 History
147(1)
8.2 Scope
147(1)
8.3 Purpose
148(1)
8.4 Pulse Waveform
148(1)
8.4.1 Pulse Waveform Equation
148(1)
8.5 Equivalent Circuit
149(1)
8.6 Test Equipment
149(1)
8.7 Test Configuration
150(3)
8.7.1 Horizontal Configuration
151(1)
8.7.2 Vertical Configuration
151(1)
8.7.3 HMM Fixture Board
152(1)
8.8 Test Sequence and Procedure
153(4)
8.8.1 Current Waveform Verification
154(1)
8.8.2 Current Probe Verification Methodology
154(2)
8.8.3 Current Probe Waveform Comparison
156(1)
8.9 Failure Mechanisms
157(1)
8.10 ESD Current Paths
158(1)
8.11 ESD Protection Circuit Solutions
158(2)
8.12 Summary and Closing Comments
160(1)
Problems
160(1)
References
161(2)
9 IEC 61000-4-5 163(11)
9.1 History
163(1)
9.2 Scope
164(1)
9.3 Purpose
164(1)
9.4 Pulse Waveform
165(1)
9.5 Equivalent Circuit
166(1)
9.6 Test Equipment
166(2)
9.7 Test Sequence and Procedure
168(1)
9.8 Failure Mechanisms
168(2)
9.9 IEC 61000-4-5 ESD Current Paths
170(1)
9.10 ESD Protection Circuit Solutions
170(1)
9.11 Alternate Test Methods
171(1)
9.12 Summary and Closing Comments
171(1)
Problems
172(1)
References
172(2)
10 Cable Discharge Event (CDE) 174(32)
10.1 History
174(1)
10.2 Scope
175(1)
10.3 Purpose
175(1)
10.4 Cable Discharge Event-Charging, Discharging, and Pulse Waveform
175(3)
10.4.1 Charging Process
176(1)
10.4.2 Discharging Process
176(1)
10.4.3 Pulse Waveform
176(1)
10.4.4 Comparison of CDE and IEC 61000-4-2 Pulse Waveform
176(2)
10.5 Equivalent Circuit
178(1)
10.6 Test Equipment
179(1)
10.6.1 Commercial Test Systems
179(1)
10.7 Test Measurement
180(5)
10.7.1 Measurement
180(1)
10.7.2 Measurement-Transmission Line Test Generators
180(1)
10.7.3 Measurement-Low-Impedance Transmission Line Waveform
181(1)
10.7.4 Schematic Capturing System Response to Reference Waveform
182(3)
10.7.5 Tapered Transmission Lines
185(1)
10.7.6 ESD Current Sensor
185(1)
10.8 Test Procedure
185(1)
10.9 Measurement of a Cable in Different Conditions
185(10)
10.9.1 Test System Configuration and Diagram
187(2)
10.9.2 Cable Configurations-Handheld Cable
189(2)
10.9.3 Cable Configuration-Taped to Ground Plane
191(1)
10.9.4 Cable Configurations-Pulse Analysis Summary
191(4)
10.10 Transient Field Measurements
195(1)
10.10.1 Transient Field Measurement of Short-Length Cable Discharge Events
195(1)
10.10.2 Antenna-Induced Voltages
195(1)
10.11 Telecommunication Cable Discharge Test System
195(5)
10.12 Cable Discharge Current Paths
200(1)
10.13 Failure Mechanisms
200(1)
10.13.1 Cable Discharge Event Failure-Connector Failure
200(1)
10.13.2 Cable Discharge Event Failure-Printed Circuit Board
201(1)
10.13.3 Cable Discharge Event Failure-Semiconductor On-Chip
201(1)
10.13.4 Cable Discharge Event (CDE)-Induced Latchup
201(1)
10.14 Cable Discharge Event (CDE) Protection
201(2)
10.14.1 RJ-45 Connectors
202(1)
10.14.2 Printed Circuit Board Design Considerations
202(1)
10.14.3 ESD Circuitry
202(1)
10.14.4 Cable Discharge Event (CDE) ESD Protection Validation
203(1)
10.15 Alternative Test Methods
203(1)
10.16 Summary and Closing Comments
204(1)
Problems
204(1)
References
204(2)
11 Latchup 206(24)
11.1 History
206(2)
11.2 Purpose
208(1)
11.3 Scope
209(1)
11.4 Pulse Waveform
209(1)
11.5 Equivalent Circuit
209(1)
11.6 Test Equipment
209(2)
11.7 Test Sequence and Procedure
211(4)
11.8 Failure Mechanisms
215(1)
11.9 Latchup Current Paths
216(1)
11.10 Latchup Protection Solutions
216(6)
11.10.1 Latchup Protection Solutions-Semiconductor Process
219(1)
11.10.2 Latchup Protection Solutions-Design Layout
219(1)
11.10.3 Latchup Protection Solutions-Circuit Design
220(1)
11.10.4 Latchup Protection Solutions-System Level Design
221(1)
11.11 Alternate Test Methods
222(2)
11.11.1 Photoemission Techniques-PICA—TLP
222(2)
11.11.2 Photoemission Techniques-CCD Method
224(1)
11.12 Single Event Latchup (SEL) Test Methods
224(1)
11.13 Summary and Closing Comments
224(3)
Problems
227(1)
References
227(3)
12 Electrical Overstress (EOS) 230(27)
12.1 History
230(2)
12.2 Scope
232(1)
12.3 Purpose
233(1)
12.4 Pulse Waveform
233(1)
12.5 Equivalent Circuit
233(1)
12.6 Test Equipment
234(1)
12.7 Test Procedure and Sequence
234(2)
12.8 Failure Mechanisms
236(4)
12.8.1 Information Gathering
236(1)
12.8.2 Failure Verification
237(1)
12.8.3 Failure Site Identification and Localization
237(1)
12.8.4 Root Cause Determination
238(1)
12.8.5 Feedback of Root Cause
238(1)
12.8.6 Corrective Actions
238(1)
12.8.7 Documentation Reports
238(1)
12.8.8 Statistical Analysis, Record Retention, and Control
238(2)
12.9 Electrical Overstress (EOS) Protection Circuit Solutions
240(9)
12.10 Electrical Overstress (EOS) Testing-TLP Method and EOS
249(3)
12.10.1 Electrical Overstress (EOS) Testing-Long Duration Transmission Line Pulse (LD-TLP) Method
250(1)
12.10.2 Electrical Overstress (EOS) Testing-Transmission Line Pulse (TLP) Method, EOS, and the Wunsch—Bell Model
250(1)
12.10.3 Electrical Overstress (EOS) Testing-Limitations of the Transmission Line Pulse (TLP) Method for the Evaluation of EOS for Systems
250(1)
12.10.4 Electrical Overstress (EOS) Testing-Electromagnetic Pulse (EMP)
251(1)
12.11 Electrical Overstress (EOS) Testing-DC and Transient Latchup Testing
252(1)
12.12 Summary and Closing Comments
252(1)
Problems
252(1)
References
253(4)
13 Electromagnetic Compatibility (EMC) 257(27)
13.1 History
257(1)
13.2 Purpose
258(1)
13.3 Scope
258(1)
13.4 Pulse Waveform
258(1)
13.5 Equivalent Circuit
259(1)
13.6 Test Equipment
259(2)
13.6.1 Commercial Test System
259(1)
13.6.2 Scanning Systems
260(1)
13.7 Test Procedures
261(1)
13.7.1 ESD/EMC Scanning Test Procedure and Method
261(1)
13.8 Failure Mechanisms
261(2)
13.9 ESD/EMC Current Paths
263(1)
13.10 EMC Solutions
264(2)
13.11 Alternative Test Methods
266(1)
13.11.1 Scanning Methodologies
266(1)
13.11.2 Testing-Susceptibility and Vulnerability
266(1)
13.11.3 EMC/ESD Scanning-Semiconductor Component and Populated Printed Circuit Board
267(1)
13.12 EMC/ESD Product Evaluation-IC Prequalification
267(1)
13.13 EMC/ESD Scanning Detection-Upset Evaluation
267(1)
13.13.1 ESD/EMC Scanning Stimulus
267(1)
13.14 EMC/ESD Product Qualification Process
268(3)
13.14.1 EMC/ESD Reproducibility
268(1)
13.14.2 EMC/ESD Failure Threshold Mapping and Histogram
268(1)
13.14.3 ESD Immunity Test-IC Level
268(3)
13.14.4 ESD Immunity Test-ATE Stage
271(1)
13.15 Alternative ESD/EMC Scanning Methods
271(5)
13.15.1 Alternative ESD/EMC Scanning Methods-Printed Circuit Board
271(3)
13.15.2 Electromagnetic Interference (EMI) Emission Scanning Methodology
274(1)
13.15.3 Radio Frequency (RF) Immunity Scanning Methodology
274(1)
13.15.4 Resonance Scanning Methodology
275(1)
13.15.5 Current Spreading Scanning Methodology
275(1)
13.16 Current Reconstruction Methodology
276(1)
13.16.1 EOS and Residual Current
276(1)
13.16.2 Printed Circuit Board (PCB) Trace Electromagnetic Emissions
276(1)
13.16.3 Test Procedure and Sequence
277(1)
13.17 Printed Circuit Board (PCB) Design EMC Solutions
277(3)
13.18 Summary and Closing Comments
280(1)
Problems
281(1)
References
282(2)
A Glossary of Terms 284(4)
B Standards 288
B.1 ESD Association
288(1)
B.2 International Organization of Standards
289(1)
B.3 IEC
289(1)
B.4 RTCA
289(1)
B.5 Department of Defense
289(1)
B.6 Military Standards
289(1)
B.7 Airborne Standards and Lightning
290
Index 2919781107167421(2085162820)
List of Contributors ix
Acknowledgements x
A Note on the Texts xi
Introduction 1(15)
Dominic Head
1 Early-Modern Diversity: The Origins of English Short Fiction 16(16)
Barbara Korte
2 Short Prose Narratives of the Eighteenth and Nineteenth Centuries 32(17)
Donald J. Newman
3 Gothic and Victorian Supernatural Tales 49(18)
Jessica Cox
4 The Victorian Potboiler: Novelists Writing Short Stories 67(17)
Sophie Gilmartin
5 Fable, Myth and Folk Tale: The Writing of Oral and Traditional Story Forms 84(16)
Andrew Harrison
6 The Colonial Short Story, Adventure and the Exotic 100(18)
Robert Hampson
7 The Yellow Book Circle and the Culture of the Literary Magazine 118(17)
Winnie Chan
8 The Modernist Short Story: Fractured Perspectives 135(17)
Claire Drewery
9 War Stories: The Short Story in the First and Second World Wars 152(16)
Ann-Marie Binhaus
1O The Short Story in Ireland to 1945: A National Literature 168(17)
Heather Ingman
11 The Short Story in Ireland since 1945: A Modernizing Tradition 185(17)
Heather Ingman
12 The Short Story in Scotland: From Oral Tale to Dialectal Style 202(17)
Timothy C. Baker
13 The Short Story in Wales: Cultivated Regionalism 219(16)
Jane Aaron
14 The Understated Art, English Style 235(17)
Dean Baldwin
15 The Rural Tradition in the English Short Story 252(17)
Dominic Head
16 Metropolitan Modernity: Stories of London 269(17)
Neal Alexander
17 Gender and Genre: Short Fiction, Feminism and Female Experience 286(18)
Sabine Coelsch-Foisner
18 Queer Short Stories: An Inverted History 304(19)
Brett Josef Grubisic
Carellin Brooks
19 Stories of Jewish Identity: Survivors, Exiles and Cosmopolitans 323(18)
Axel Stahler
20 New Voices: Multicultural Short Stories 341(17)
Abigail Ward
21 Settler Stories: Postcolonial Short Fiction 358(19)
Victoria Kuttainen
22 After Empire: Postcolonial Short Fiction and the Oral Tradition 377(18)
John Thieme
23 Ghost Stories and Supernatural Tales 395(16)
Ruth Robbins
24 The Detective Story: Order from Chaos 411(18)
Andrew Maunder
25 Frontiers: Science Fiction and the British Marketplace 429(18)
Paul March-Russell
26 Weird Stories: The Potency of Horror and Fantasy 447(17)
Roger Luckhurst
27 Experimentalism: Self-Reflexive and Postmodernist Stories 464(17)
David James
28 Satirical Stories: Estrangement and Social Critique 481(17)
Sandie Byrne
29 Comedic Short Fiction 498(15)
Richard Bradford
30 Short Story Cycles: Between the Novel and the Story Collection 513(17)
Gerald Lynch
31 The Novella: Between the Novel and the Story 530(17)
Gerri Kimber
32 The Short Story Visualized: Adaptations and Screenplays 547(17)
Linda Costanzo Cahir
33 The Short Story Anthology: Shaping the Canon 564(17)
Lynda Prescott
34 The Institution of Creative Writing 581(17)
Ailsa Cox
35 Short Story Futures 598(17)
Julian Murphet
Select Bibliography 615(10)
Index 625
Dr Steven H. Voldman, IEEE Fellow, Vermont, USA Dr. Steven H. Voldman is the first IEEE Fellow in the field of electrostatic discharge (ESD) for "Contributions in ESD protection in CMOS, Silicon On Insulator and Silicon Germanium Technology." Voldman was a member of the semiconductor development of IBM for 25 years as well as a consultant for TSMC, and Samsung Electronics. Dr. Voldman initiated the first transmission line pulse (TLP) standard development team, and a participant in the JEDEC-ESD Association standards harmonization of the human body model (HBM) Standard. From 2000 to 2013, as Chairman of the ESD Association Work Group on TLP and very-fast TLP (VF-TLP), his team was responsible for initiating the first standard practice and standards for TLP and VF-TLP. He initiated the "ESD on Campus" program which was established to bring ESD lectures and interaction to university faculty and students internationally; the ESD on Campus program has reached over 40 universities in the United States, Korea, Singapore, Taiwan, Malaysia, Philippines, Thailand, India, and China. Dr. Voldman teaches short courses and tutorials on ESD, latchup, patenting, and invention.
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