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E-raamat: Essential Guide to Serial ATA and SATA Express

  • Formaat: 496 pages
  • Ilmumisaeg: 09-Oct-2014
  • Kirjastus: Apple Academic Press Inc.
  • Keel: eng
  • ISBN-13: 9781482243338
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Essential Guide to Serial ATA and SATA ExpressSuurem pilt
  • Formaat: 496 pages
  • Ilmumisaeg: 09-Oct-2014
  • Kirjastus: Apple Academic Press Inc.
  • Keel: eng
  • ISBN-13: 9781482243338
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Deming presents technically adept support, design, development, and deployment specialists working with Enterprise or Client storage solutions with a guide to architecting, analyzing, and troubleshooting data center applications utilizing SATA or SATA Express technology. The author provides readers with an introduction to SATA and serial ATA technology, systems and applications, SATA technical attributes, SATA application layer, transport layer, link layer, physical layer, and error handling, cable connectors, port multipliers and selectors, and software and drivers. David A. Deming is the President and Chief Technologist at Solution Technology, a technology consultancy. Annotation ©2015 Ringgold, Inc., Portland, OR (protoview.com)

Used in laptop and desktop computers, low-end servers, and mobile devices, Serial ATA (Advance Technology Attachment), or SATA, is the pervasive disk storage technology in use today. SATA has also penetrated the enterprise computing environment by adding hardware components for fail-over, extending command processing capabilities, and increasing device performance and link speeds. If you work in a data center or manage your company’s storage resources, you will likely encounter storage solutions that require SATA software or hardware.

In this book, leading storage networking technologist David Deming presents a comprehensive guide to designing, analyzing, and troubleshooting any SATA or SATA Express (SATAe) storage solution. Written by an engineer, this book is for those who aren't afraid of digging into the technical details. It explains how SATA/SATAe powers data center applications and how it influences and interacts with all protocol layers and system components.

This book covers all of the tasks associated with installing, configuring, and managing SATA/SATAe storage applications. If you are a test engineer, design engineer, system architect, or even a technically skilled gamer who likes to build your own systems, this book will answer your technical questions about SATA/SATAe. With this book, you should have everything you need to implement a SATA or SATAe storage solution.

Foreword xiii
Preface xv
Acknowledgments xvii
About the Author xix
Acronyms and Glossary xxi
Chapter 1 Introduction 1(30)
Objectives
1(1)
1.1 Introduction to SATA
1(3)
1.1.1 Serial Interface Advantage
3(1)
1.2 The Move to Serial Technology
4(1)
1.2.1 Serial ATA Goals and Objectives
4(1)
1.2.2 SATA Benefits
5(1)
1.3 Almost Exactly 10 Years Later
5(4)
1.3.1 Introduction to SATA Express
6(3)
1.4 Storage Evolution
9(6)
1.5 Serial ATA System Connection Model
15(6)
1.5.1 SATA Connectivity
16(2)
1.5.2 External SATA Storage
18(1)
1.5.3 SATA High Availability
19(2)
1.6 SATA Applications-More than Disk Storage
21(9)
1.6.1 Client and Enterprise SATA Devices
21(2)
1.6.2 mSATA
23(1)
1.6.3 M.2 SATA
24(3)
1.6.4 microSSDTM
27(1)
1.6.5 SATA Universal Storage Module
28(2)
1.7 Summary
30(1)
Chapter 2 SATA Technical Overview 31(50)
Objectives
31(1)
2.1 What Is ATA?
32(1)
2.1.1 Physical Interface
32(1)
2.2 Specifications and Standards
33(7)
2.2.1 Industry Standards
33(4)
2.2.2 SATA Specifications
37(3)
2.3 SATA Layered Architecture
40(1)
2.4 The I/O Register Model
41(6)
2.4.1 Host and Device Register
43(1)
2.4.2 Parallel Register Operations
43(3)
2.4.3 PATA I/O Process Flow
46(1)
2.5 Register Formats
47(4)
2.5.1 Command Register
47(1)
2.5.2 Status Register
48(1)
2.5.3 Error Register
49(2)
2.5.4 Device Register
51(1)
2.6 CHS and LBA Addressing
51(3)
2.6.1 CHS Addressing
51(1)
2.6.2 LBA Addressing
51(3)
2.7 ATA Protocols
54(3)
2.7.1 Data Transfer Modes - PIO
54(1)
2.7.2 Data Transfer Modes-DMA
55(1)
2.7.3 Parallel ATA Emulation
56(1)
2.8 SATA Technical Overview
57(2)
2.8.1 Serial Links
57(1)
2.8.2 Differential Signaling
58(1)
2.9 Encoding
59(2)
2.9.1 8b10b Encoding
59(1)
2.9.2 Encoding Characteristics
59(2)
2.10 SATA Primitives and Data Words
61(2)
2.10.1 SATA Primitives
62(1)
2.11 Idle Serial Links
63(1)
2.12 Frame Transmission
64(2)
2.13 Link Layer Protocol
66(6)
2.13.1 Link Layer Protocol Summary
69(1)
2.13.2 Transport Layer Protocol
70(2)
2.14 Application Layer
72(2)
2.14.1 CHS to LBA Translation
73(1)
2.14.2 General Feature Set Commands
74(1)
2.15 Summary
74(1)
2.16 Review Questions
75(6)
Chapter 3 SATA Application Layer 81(122)
Objectives
81(1)
3.1 SATA Application/Command Layer
82(2)
3.1.1 Command Set
82(1)
3.1.2 Register Delivered Command Sector Addressing
83(1)
3.2 Command Codes from ATA/ATAPI Command Set R41
84(14)
3.2.1 General Feature Set Commands
90(1)
3.2.2 Optional General Feature Set Commands
91(1)
3.2.3 PACKET General Feature Set Commands
91(1)
3.2.4 Unique PACKET Command Feature Set
92(1)
3.2.5 Power Management Feature Set
92(1)
3.2.6 PACKET Power Management Feature Set
93(1)
3.2.7 Security Mode Feature Set
93(1)
3.2.8 SMART Feature Set Commands
93(1)
3.2.9 Removable Media Status Notification Feature Set
94(1)
3.2.10 Removable Media Feature Set
94(1)
3.2.11 CompactFlash™ Association (CFA) Feature Set
95(1)
3.2.12 48-Bit Address Feature Set
96(1)
3.2.13 Streaming Feature Set
96(1)
3.2.14 General Purpose Logging Feature Set
97(1)
3.2.15 Overlapped Feature Set
97(1)
3.3 Command Descriptions
98(103)
3.3.1 Command Overview
98(1)
3.3.2 Device Configuration
99(102)
3.4 Review Questions
201(2)
Chapter 4 SATA Transport Layer 203(62)
Objectives
203(1)
4.1 SATA Transport Layer
203(17)
4.1.1 Transport Layer Services
203(1)
4.1.2 Frame Information Structure (FIS)
204(1)
4.1.3 FIS Types
204(1)
4.1.4 Register - Host to Device FIS
204(2)
4.1.5 Register - Device to Host FIS
206(4)
4.1.6 Set Device Bits FIS
210(1)
4.1.7 First-Party DMA Setup FIS
211(1)
4.1.8 DMA Activate FIS
211(1)
4.1.9 SATA II Changes to DMA Transport
212(3)
4.1.10 Data FIS
215(1)
4.1.11 BIST Activate FIS
216(2)
4.1.12 PIO Setup FIS
218(1)
4.1.13 Changes to FISes for Port Multipliers
219(1)
4.2 Serial Interface Host Adapter Registers Overview
220(22)
4.2.1 SCR Mapping and Organization
220(1)
4.2.2 SStatus, SError, and SControl Registers
220(7)
4.2.3 Command Processing Examples
227(1)
4.2.4 Legacy DMA Read by Host from Device
227(1)
4.2.5 Legacy DMA Write by Host to Device
228(1)
4.2.6 PIO Data Read from the Device
229(1)
4.2.7 PIO Data Write to the Device
230(3)
4.2.8 WRITE DMA QUEUED Example
233(1)
4.2.9 ATAPI PACKET Commands with PIO Data-In
234(2)
4.2.10 ATAPI PACKET Commands with PIO Data-Out
236(1)
4.2.11 ATAPI PACKET Commands with DMA Data-In
237(1)
4.2.12 ATAPI PACKET Commands with DMA Data-Out
238(1)
4.2.13 First-Party DMA Read of Host Memory by Device
239(1)
4.2.14 First-Party DMA Write of Host Memory by Device
240(1)
4.2.15 PIO Data Read from the Device - Odd Word Count
241(1)
4.2.16 PIO Data Write to the Device - Odd Word Count
241(1)
4.2.17 First-Party DMA Read of Host Memory by Device - Odd Word Count
241(1)
4.2.18 First-Party DMA Write of Host Memory by Device - Odd Word Count
242(1)
4.3 Native Command Queuing
242(15)
4.3.1 Introduction to NCQ
243(1)
4.3.2 Benefits of Native Command Queuing (NCQ)
244(2)
4.3.3 Detailed Description of NCQ
246(5)
4.3.4 How Applications Take Advantage of Queuing
251(1)
4.3.5 Conclusion
252(1)
4.3.6 NCQ Example
252(5)
4.4 NCQ Queue Management
257(3)
4.4.1 ABORT NCQ QUEUE Subcommand (Oh)
258(1)
4.4.2 NCQ Deadline Handling Subcommand (1h)
259(1)
4.5
Chapter Review
260(5)
Chapter 5 SATA Link Layer 265(32)
Objectives
265(1)
5.1 Link Layer Responsibilities
265(1)
5.1.1 Frame Transmission Topics
265(1)
5.1.2 Frame Reception Topics
266(1)
5.2 Transmission Methodology
266(2)
5.2.1 SATA Structures
267(1)
5.2.2 DWORDs
267(1)
5.2.3 Primitive Structure
268(1)
5.3 Frame Structure
268(2)
5.4 Primitives
270(8)
5.4.1 Primitive Encoding
271(1)
5.4.2 Detailed Primitives Descriptions
272(6)
5.5 Scrambling
278(3)
5.5.1 Frame Content Scrambling
278(3)
5.6 Link Layer Traces
281(1)
5.7 Encoding Method
282(10)
5.7.1 Notation and Conventions
282(1)
5.7.2 Encoding Characteristics
282(3)
5.7.3 Running Disparity
285(1)
5.7.4 8b10b Valid Encoded Characters
286(6)
5.8 CRC Calculation
292(1)
5.9 Review Questions
292(5)
Chapter 6 Physical Layer 297(34)
Objectives
297(1)
6.1 PHY Layer Services
297(1)
6.2 Out of Band (OOB) Signaling
298(13)
6.2.1 OOB Signaling Protocol
299(1)
6.2.2 Power-Up and COMRESET Timing
300(1)
6.2.3 Link Speeds
301(3)
6.2.4 Resets and Signatures
304(1)
6.2.5 OOB Signal Detection Logic
305(2)
6.2.6 Interface Power States
307(4)
6.3 BIST (Built-In Self-Test)
311(6)
6.3.1 Loopback Testing
311(1)
6.3.2 Loopback-Far End Retimed
311(2)
6.3.3 Loopback-Far-End Analog (Optional)
313(1)
6.3.4 Loopback-Near-End Analog (Optional)
313(1)
6.3.5 Impedance Matching
314(1)
6.3.6 Physical Layer Electronics (PHY)
315(2)
6.4 Electrical Specifications
317(11)
6.4.1 Electrical Goals, Objectives, and Constraints
320(3)
6.4.2 Rise/Fall Times
323(5)
6.5 Review Questions
328(3)
Chapter 7 Error Handling 331(14)
Objectives
331(1)
7.1 Error Handling
331(8)
7.1.1 Error Handling Responses
332(1)
7.1.2 Phy Error Handling Overview
332(2)
7.1.3 Link Error Handling Overview
334(1)
7.1.4 Transport Error Handling
335(3)
7.1.5 Software Error Handling Overview
338(1)
7.2 State Diagram Conventions
339(4)
7.2.1 Power-on and COMRESET Protocol Diagram
341(1)
7.2.2 Host Phy Initialization State Machine
342(1)
7.3 Review
343(2)
Chapter 8 Cables and Connectors 345(34)
Objectives
345(1)
8.1 SATA Connectivity for Device Storage
345(16)
8.1.1 Client and Enterprise SATA Devices
345(5)
8.1.2 Micro SATA
350(1)
8.1.3 mSATA
351(5)
8.1.4 LI F-SATA
356(2)
8.1.5 microSSDTM
358(1)
8.1.6 M.2 SATA
358(3)
8.2 SATA Universal Storage Module (USM)
361(2)
8.3 SATA Cabling
363(7)
8.3.1 Cable Assemblies
364(1)
8.3.2 Internal 1 m Cabled Host to Device
365(2)
8.3.3 SATA Cable
367(1)
8.3.4 External SATA
368(2)
8.4 SATA Express
370(6)
8.4.1 SATA Express Connector Goals
370(1)
8.4.2 SATA Express Is Pure PCIe
370(1)
8.4.3 SATA Express Scope
371(5)
8.5 Hot Plugging
376(1)
8.6 Review
377(2)
Chapter 9 Port Multipliers and Selectors 379(46)
Objectives
379(1)
9.1 Port Multiplier
379(2)
9.1.1 Port Multiplier Characteristics
380(1)
9.2 PM Operational Overview
381(6)
9.2.1 Addressing Mechanism
381(5)
9.2.2 Policies
386(1)
9.3 FIS Delivery Mechanisms
387(3)
9.3.1 Starting a FIS Transmission
387(1)
9.3.2 Booting with Legacy Software
388(1)
9.3.3 Hot Plug Events
389(1)
9.4 Link Power Management
390(1)
9.5 Reducing Context Switching Complexity
390(1)
9.6 Error Handling and Recovery
391(4)
9.6.1 Command Timeout
391(1)
9.6.2 Disabled Device Port
391(1)
9.6.3 Invalid Device Port Address
391(1)
9.6.4 Invalid CRC for Device-Initiated Transfer
392(1)
9.6.5 Data Corruption
392(1)
9.6.6 Command-Based Switching
393(2)
9.7 Port Multiplier Registers
395(5)
9.7.1 General Status and Control Registers
395(1)
9.7.2 Status Information and Control
396(2)
9.7.3 Features Supported
398(1)
9.7.4 Port Status and Control Registers
399(1)
9.8 Port Multiplier Command
400(4)
9.8.1 Read Port Multiplier
400(2)
9.8.2 Write Port Multiplier
402(2)
9.9 Serial ATA Superset Registers Enhancements
404(3)
9.9.1 Resets and Software Initialization Sequences
405(2)
9.10 Examples of Software Initialization Sequences
407(1)
9.10.1 Port Multiplier Aware Software
407(1)
9.10.2 Port Multiplier Discovery and Device Enumeration
407(1)
9.11 Switching Type Examples
408(2)
9.11.1 Command-Based Switching
409(1)
9.11.2 FIS-Based Switching
409(1)
9.12 Port Selectors
410(5)
9.12.1 Port Selector Definitions, Abbreviations, and Conventions
410(1)
9.12.2 Port Selector Overview
411(1)
9.12.3 Active Port Selection
411(3)
9.12.4 Side-Band Port Selection
414(1)
9.12.5 Behavior During a Change of Active Port
414(1)
9.13 Behavior and Policies
415(2)
9.13.1 Control State Machine
415(2)
9.14 BIST Support
417(2)
9.14.1 Flow Control Signaling Latency
417(1)
9.14.2 Power Management
417(2)
9.15 Power-up and Resets
419(1)
9.15.1 Power-up
419(1)
9.15.2 Resets
419(1)
9.16 Host Implementation
419(1)
9.16.1 Software Method for Protocol-Based Selection (Informative)
419(1)
9.17 Summary
420(5)
Chapter 10 Software and Drivers 425(28)
Objectives
425(1)
10.1 Storage I/O Stack
426(3)
10.1.1 I/O Manager
427(1)
10.1.2 File System
427(1)
10.1.3 Volume Manager
427(1)
10.1.4 Hardware
428(1)
10.2 SATA and SATA Express
429(2)
10.3 SATA Configurations
431(1)
10.4 Advanced Host Channel Interface
432(3)
10.4.1 System Memory Structure
433(1)
10.4.2 AHCI Encompasses a PCI Device
433(2)
10.5 HBA Configuration Registers
435(6)
10.5.1 HBA Memory Registers
437(4)
10.6 System Memory Model
441(3)
10.6.1 Received FIS Structure
441(1)
10.6.2 Command List Structure
441(3)
10.7 Summary
444(9)
10.7.1 SATA and SATA Express Architectures Review
444(1)
10.7.2 Advanced Host Channel Interface (AHCI) Review
444(1)
10.7.3 PCI Header and Configuration Space Review
445(1)
10.7.4 Memory Registers Review
446(3)
10.7.5 HBA Memory Space Usage Review
449(1)
10.7.6 Port Memory Usage Review
449(2)
10.7.7 Command List Structure Review
451(2)
Appendix A:
Chapter Review Answers		 453(4)
Index 457
David Deming is the president and chief technologist of Solution Technology. With a degree in electronics engineering and more than two decades of industry experience, David has designed many courses covering a wide range of storage and networking technologies. Davids organization is the industrys leading supplier of storage technology education, and David has personally trained over 50,000 engineers worldwide. David has authored over a dozen storage technology-related publications and is an expert instructional designer. He has assisted many companies with detailed job and task analysis, resulting in high-stakes certification programs and curriculum.





David is an active member of numerous industry associations and committees. In the early stages of Fibre Channel technology, David organized and coordinated the efforts of the Interoperability Testing Program for the Fibre Channel Industry Association (FCIA). As interoperability program chair, David played a major role in organizing competing switch vendor efforts to create the first ever FC switch interoperability demonstration. This technology accomplishment was the centerpiece of the Storage Networking Industry Association (SNIA) Technology Center grand opening in Colorado Springs, Colorado. David also authorized the SANmark program, which became the cornerstone test cases developed and administered by the University of New Hampshire Interoperability Lab (UNH-IOL).





David architected and designed the first-ever multi-vendor (heterogeneous) Fibre Channel SAN featured in Computer Technology Review, and he coordinated the industrys first and largest Interoperability Lab demonstration for Storage Networking World. David has been a voting member of the NCITS T11 Fibre Channel standards committee and has served on T10 (SCSI & SAS) and T10.1 (SSA) standards committees. He is a founder and active member of the SNIA Education Committee and Certification Task Force for which, i
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