Muutke küpsiste eelistusi

E-raamat: FinFET Devices for VLSI Circuits and Systems

(Santa Clara University, California, USA)
  • Formaat: 338 pages
  • Ilmumisaeg: 15-Jul-2020
  • Kirjastus: CRC Press
  • Keel: eng
  • ISBN-13: 9780429998096
Teised raamatud teemal:
  • Formaat - PDF+DRM
  • Hind: 64,99 €*
  • * hind on lõplik, st. muud allahindlused enam ei rakendu
  • Lisa ostukorvi
  • Lisa soovinimekirja
  • See e-raamat on mõeldud ainult isiklikuks kasutamiseks. E-raamatuid ei saa tagastada.
FinFET Devices for VLSI Circuits and SystemsSuurem pilt
  • Formaat: 338 pages
  • Ilmumisaeg: 15-Jul-2020
  • Kirjastus: CRC Press
  • Keel: eng
  • ISBN-13: 9780429998096
Teised raamatud teemal:

DRM piirangud

  • Kopeerimine (copy/paste):

    ei ole lubatud

  • Printimine:

    ei ole lubatud

  • Kasutamine:

    Digitaalõiguste kaitse (DRM)
    Kirjastus on väljastanud selle e-raamatu krüpteeritud kujul, mis tähendab, et selle lugemiseks peate installeerima spetsiaalse tarkvara. Samuti peate looma endale  Adobe ID Rohkem infot siin. E-raamatut saab lugeda 1 kasutaja ning alla laadida kuni 6'de seadmesse (kõik autoriseeritud sama Adobe ID-ga).

    Vajalik tarkvara
    Mobiilsetes seadmetes (telefon või tahvelarvuti) lugemiseks peate installeerima selle tasuta rakenduse: PocketBook Reader (iOS / Android)

    PC või Mac seadmes lugemiseks peate installima Adobe Digital Editionsi (Seeon tasuta rakendus spetsiaalselt e-raamatute lugemiseks. Seda ei tohi segamini ajada Adober Reader'iga, mis tõenäoliselt on juba teie arvutisse installeeritud )

    Seda e-raamatut ei saa lugeda Amazon Kindle's. 

"To surmount the continuous scaling challenges of MOSFET devices, FinFETs have emerged as the real alternative for use as the next generation device for IC fabrication technology. The objective of the book is to provide the basic theory and operating principles of FinFET devices and technology, an overview of FinFET device architecture and manufacturing processes, detailed formulation of FinFET electrostatic and dynamic device characteristics for IC design and manufacturing. Thus, this book caters to practicing engineers transitioning to FinFET technology and prepares the next generation device engineers and academic experts on mainstream device technology at the nanometer-nodes"--

To surmount the continuous scaling challenges of MOSFET devices, FinFETs have emerged as the real alternative for use as the next generation device for IC fabrication technology. The objective of this book is to provide the basic theory and operating principles of FinFET devices and technology, an overview of FinFET device architecture and manufacturing processes, and detailed formulation of FinFET electrostatic and dynamic device characteristics for IC design and manufacturing. Thus, this book caters to practicing engineers transitioning to FinFET technology and prepares the next generation of device engineers and academic experts on mainstream device technology at the nanometer-nodes.

Preface xv
Author xix
Chapter 1 Introduction
1(24)
1.1 Fin Field-Effect Transistors
1(1)
1.2 Overview of MOSFET Devices for Integrated Circuit Manufacturing
1(7)
1.2.1 Challenges of MOSFET Scaling at the Nanometer Node
4(1)
1.2.1.1 Leakage Current in Short Channel MOSFETs
4(2)
1.2.1.2 Variability in MOSFETs
6(1)
1.2.2 Physics of MOSFET Scaling Challenges
7(1)
1.3 Alternative Device Concepts
8(5)
1.3.1 Undoped or Lightly Doped Channel MOSFETs
9(1)
1.3.1.1 Deeply Depleted Channel MOSFETs
9(1)
1.3.1.2 Buried-Halo MOSFETs
10(1)
1.3.2 Thin-Body Field-Effect Transistors
11(1)
1.3.2.1 Single-Gate Ultrathin-Body Field-Effect Transistors
11(1)
1.3.2.2 Multiple-Gate Field-Effect Transistors
12(1)
1.4 FinFET Devices for VLSI Circuits and Systems
13(2)
1.5 A Brief History of FinFET Devices
15(3)
1.6 Summary
18(1)
References
19(6)
Chapter 2 Fundamentals of Semiconductor Physics
25(60)
2.1 Introduction
25(1)
2.2 Semiconductor Physics
25(30)
2.2.1 Energy Band Model
26(1)
2.2.2 Carrier Statistics
27(2)
2.2.3 Intrinsic Semiconductors
29(1)
2.2.3.1 Intrinsic Carrier Concentration
29(2)
2.2.3.2 Effective Mass of Electrons and Holes
31(1)
2.2.4 Extrinsic Semiconductors
31(2)
2.2.4.1 Fermi Level in Extrinsic Semiconductor
33(2)
2.2.4.2 Fermi Level in Degenerately Doped Semiconductor
35(1)
2.2.4.3 Electrostatic Potential in Semiconductor and Carrier Concentration
36(2)
2.2.4.4 Quasi-Fermi Level
38(1)
2.2.5 Carrier Transport in Semiconductors
39(1)
2.2.5.1 Drift of Carriers: Carrier Motion in Electric Field
39(5)
2.2.5.2 Diffusion of Carriers
44(3)
2.2.6 Generation-Recombination of Carrier
47(1)
2.2.6.1 Injection Level
48(1)
2.2.6.2 Recombination Processes
48(3)
2.2.7 Basic Semiconductor Equations
51(1)
2.2.7.1 Poisson's Equation
51(2)
2.2.7.2 Transport Equations
53(1)
2.2.7.3 Continuity Equations
53(2)
2.3 Theory of n-Type and p-Type Semiconductors in Contact
55(26)
2.3.1 Basic Features of pn-Junctions
55(2)
2.3.2 Built-Iin Potential
57(1)
2.3.3 Step Junctions
58(1)
2.3.3.1 Electrostatics
58(4)
2.3.4 pn-Junctions under External Bias
62(1)
2.3.4.1 One-Sided Step Junction
63(2)
2.3.5 Carrier Transport Across pn-Junctions
65(1)
2.3.5.1 Relationship between Minority Carrier Density and Junction Potential
65(4)
2.3.6 pn-Junctions I - V Characteristics
69(2)
2.3.6.1 Temperature Dependence of pn-Junction Leakage Current
71(1)
2.3.6.2 Limitations of pn-Junction Current Equation
72(2)
2.3.6.3 Bulk Resistance
74(1)
2.3.6.4 Junction Breakdown Voltage
75(1)
2.3.7 pn-Junction Dynamic Behavior
76(1)
2.3.7.1 Junction Capacitance
77(2)
2.3.7.2 Diffusion Capacitance
79(1)
2.3.7.3 Small-Signal Conductance
80(1)
2.3.8 pn-Junction Equivalent Circuit
80(1)
2.4 Summary
81(1)
References
82(3)
Chapter 3 Multiple-Gate Metal-Oxide-Semiconductor (MOS) System
85(48)
3.1 Introduction
85(1)
3.2 Multigate MOS Capacitors at Equilibrium
85(14)
3.2.1 Properties of Isolated Metal, Oxide, and Semiconductor Materials
87(1)
3.2.1.1 Workfunction
88(2)
3.2.2 Metal, Oxide, and Semiconductor Materials in Contact Forming MOS Systems
90(1)
3.2.2.1 MOS Systems with MG Workfunction at Silicon Band-Edges
90(2)
3.2.2.2 MOS Systems with Silicon-Midgap MG Workfunction
92(2)
3.2.3 Oxide Charges
94(1)
3.2.3.1 Interface Trapped Charge
95(1)
3.2.3.2 Fixed Oxide Charge
95(1)
3.2.3.3 Oxide Trapped Charge
95(1)
3.2.3.4 Mobile Ionic Charge
96(1)
3.2.4 Effect of Oxide Charges on Energy Band Structure: Flat Band Voltage
96(1)
3.2.5 Surface Potential
97(2)
3.3 MOS Capacitor Under Applied Bias
99(5)
3.3.1 Accumulation
101(1)
3.3.2 Depletion
102(1)
3.3.3 Inversion
103(1)
3.4 Multigate MOS Capacitor Systems: Mathematical Analysis
104(24)
3.4.1 Poisson's Equation
105(3)
3.4.2 Electrostatic Potentials and Charge Distribution
108(1)
3.4.2.1 Induced Charge in Semiconductor
108(4)
3.4.2.2 Formulation of Surface Potential
112(6)
3.4.2.3 Threshold Voltage
118(4)
3.4.2.4 Surface Potential Function
122(3)
3.4.2.5 Unified Expression for Inversion Charge Density
125(3)
3.5 Quantum Mechanical Effect
128(2)
3.6 Summary
130(1)
References
130(3)
Chapter 4 Overview of FinFET Device Technology
133(18)
4.1 Introduction
133(1)
4.2 FinFET Manufacturing Technology
134(1)
4.3 Bulk-FinFET Fabrication
135(11)
4.3.1 Starting Material
136(1)
4.3.2 Well Formation
136(1)
4.3.2.1 p-Well Formation
136(1)
4.3.2.2 n-Well Formation
136(1)
4.3.3 Fin Patterning: Spacer Etch Technique
136(1)
4.3.3.1 Mandrel Patterning
137(1)
4.3.3.2 Oxide Spacer Formation
138(1)
4.3.3.3 Silicon Fin Formation
138(1)
4.3.4 Alternative Well Formation Process
139(1)
4.3.5 Gate Definition: Polysilicon Dummy Gate Formation
139(1)
4.3.6 Source-Drain Extensions Processing
140(1)
4.3.6.1 nFinFET Source-Drain Extension Formation
140(1)
4.3.6.2 pFinFET Source-Drain Extension Formation
140(1)
4.3.7 Raised Source-Drain Processing
141(1)
4.3.7.1 SiGe pFinFET Raised Source-Drain Formation
141(1)
4.3.7.2 SiC <<FinFET Raised Source-Drain Formation
142(1)
4.3.7.3 Raised Source-Drain Silicidation
142(1)
4.3.8 Replacement Metal Gate Formation
143(1)
4.3.8.1 Polysilicon Dummy Gate Removal
143(1)
4.3.8.2 High-* Gate Dielectric Deposition
144(1)
4.3.8.3 Metal Gate Formation
144(1)
4.3.9 Self-Aligned Contact Formation
144(1)
4.3.9.1 Metallization
145(1)
4.4 SOI-FinFET Process Flow
146(2)
4.4.1 Starting Material
146(1)
4.4.2 Fin Patterning: Spacer Etch Technique
146(1)
4.4.2.1 Mandrel Patterning
146(1)
4.4.2.2 Oxide Spacer Formation
146(1)
4.4.2.3 Silicon Fin Formation
147(1)
4.4.3 Comparison of Bulk-Silicon FinFET and SOI-FinFET Fabrication Technology
147(1)
4.5 Summary
148(1)
References
148(3)
Chapter 5 Large Geometry FinFET Device Operation
151(32)
5.1 Introduction
151(1)
5.2 Basic Features of FinFET Devices
152(3)
5.3 FinFET Device Operation
155(1)
5.4 Drain Current Formulation
156(24)
5.4.1 Derivation of Electrostatic Potential
161(7)
5.4.2 Continuous Drain Current Equation for Symmetric DG-FinFETs
168(4)
5.4.3 Regional Drain Current Formulation for Symmetric DG-FinFETs
172(1)
5.4.3.1 Threshold Voltage Formulation
172(1)
5.4.3.2 Linear Region lis Equation
173(2)
5.4.3.3 Saturation Region Iis Equation
175(1)
5.4.3.4 Subthreshold Conduction
176(4)
5.5 Summary
180(1)
References
180(3)
Chapter 6 Small Geometry FinFETs: Physical Effects on Device Performance
183(32)
6.1 Introduction
183(1)
6.2 Short-Channel Effects on Threshold Voltage
183(9)
6.2.1 Formulation of Natural Length
184(6)
6.2.2 Channel Potential
190(2)
6.2.3 Threshold Voltage Roll-Off
192(1)
6.2.4 DIBL Effect on Threshold Voltage
192(1)
6.3 Quantum Mechanical Effects
192(7)
6.3.1 Volume Inversion
193(2)
6.3.2 QM Effect on Mobility
195(1)
6.3.3 QM Effect on Threshold Voltage
195(3)
6.3.4 QM Effect on Drain Current
198(1)
6.4 Surface Mobility
199(5)
6.5 High Field Effects
204(5)
6.5.1 Velocity Saturation
204(3)
6.5.2 Channel Length Modulation
207(2)
6.6 Output Resistance
209(2)
6.7 Summary
211(1)
References
211(4)
Chapter 7 Leakage Currents in FinFETs
215(16)
7.1 Introduction
215(1)
7.2 Subthreshold Leakage Currents
215(2)
7.3 Gate-Induced Drain and Source Leakage Currents
217(4)
7.3.1 Formulation of Gate-Induced Drain Leakage Current
218(3)
7.3.2 Formulation of Gate-Induced Source Leakage Current
221(1)
7.4 Impact Ionization Current
221(5)
7.5 Source-Drain pn-Junction Leakage Current
226(1)
7.6 Gate Oxide Tunneling Leakage Currents
226(1)
7.7 Summary
227(1)
References
228(3)
Chapter 8 Parasitic Elements in FinFETs
231(26)
8.1 Introduction
231(1)
8.2 Source-Drain Parasitic Resistance
232(14)
8.2.1 Raised Source-Drain FinFET Structure
232(2)
8.2.2 Components of Source-Drain Series Resistance
234(1)
8.2.2.1 Contact Resistance
235(2)
8.2.2.2 Spreading Resistance
237(3)
8.2.2.3 Source-Drain Extension Resistance
240(6)
8.3 Gate Resistance
246(2)
8.4 Parasitic Capacitance Elements
248(3)
8.4.1 Gate Overlap Capacitance
248(1)
8.4.2 Fringe Capacitance
249(1)
8.4.2.1 Fin-to-Gate Fringe Capacitance
250(1)
8.4.2.2 Gate-to-Contact Fringe Capacitance
250(1)
8.5 Source-Drain pn-Junction Capacitance
251(4)
8.5.1 Reverse-Bias Capacitance
252(2)
8.5.2 Forward Bias Capacitance
254(1)
8.6 Summary
255(1)
References
255(2)
Chapter 9 Challenges to FinFET Process and Device Technology
257(20)
9.1 Introduction
257(1)
9.2 Process Technology Challenges
257(8)
9.2.1 Lithography Challenges
257(1)
9.2.1.1 ArF Lithography with Multi-Patterning
258(1)
9.2.1.2 Extreme Ultraviolet Lithography
258(1)
9.2.2 Process Integration Challenges
259(1)
9.2.2.1 Precise and Uniform Fin Patterning
259(1)
9.2.2.2 Gate and Spacer Patterning
259(1)
9.2.2.3 Uniform Junction Formation in Fin
260(1)
9.2.2.4 Stress Engineering
260(1)
9.2.2.5 High-k Dielectric and Metal Gate
261(1)
9.2.2.6 Variability Control
262(1)
9.2.2.7 Spatial Challenges
262(1)
9.2.3 Dopant Implantation Challenges
263(1)
9.2.3.1 Conformal Doping
263(1)
9.2.3.2 Damage Control
263(1)
9.2.4 The Etching Challenges
264(1)
9.2.4.1 Depth Loading Control of Fin Etching
264(1)
9.2.4.2 Gate Etch Control
264(1)
9.2.4.3 STI Process for Gate
264(1)
9.2.4.4 Gate Process
264(1)
9.3 Device Technology Challenges
265(6)
9.3.1 Multiple Threshold Voltage Devices
265(2)
9.3.2 Width Quantization
267(1)
9.3.3 Crystal Orientation
268(2)
9.3.4 Source-Drain Series Resistance
270(1)
9.4 Challenges in FinFET Circuit Design
271(1)
9.5 Summary
271(1)
References
272(5)
Chapter 10 FinFET Compact Models for Circuit Simulation
277(32)
10.1 Introduction
277(1)
10.2 Compact Device Model
277(2)
10.3 Common Multiple-Gate Compact FinFET Model
279(17)
10.3.1 Core Model
279(1)
10.3.1.1 Electrostatics
279(7)
10.3.1.2 Drain Current Model
286(2)
10.3.2 Modeling Real Device Effects
288(1)
10.3.2.1 Short-Channel Effects
288(3)
10.3.2.2 Quantum Mechanical Effects
291(3)
10.3.2.3 Mobility Degradation
294(1)
10.3.2.4 Velocity Saturation
295(1)
10.3.2.5 Source-Drain Series Resistance
295(1)
10.4 Dynamic Model
296(2)
10.4.1 Common Multigate C - V Model
296(2)
10.5 Threshold Voltage Variability
298(8)
10.6 Summary
306(1)
References
306(3)
Index 309
Samar K. Saha received a PhD in Physics from Gauhati University, India, and

MS in Engineering Management from Stanford University, CA. Currently, he is an

Adjunct Professor in the Electrical Engineering Department at Santa Clara University,

CA, and Chief Research Scientist at Prospicient Devices, CA. Since 1984, he has

worked in various technical and management positions for National Semiconductor,

LSI Logic, Texas Instruments, Philips Semiconductors, Silicon Storage Technology,

Synopsys, DSM Solutions, Silterra USA, and SuVolta. He has also worked as a

faculty member in the Electrical Engineering Departments at Southern Illinois

University at Carbondale, IL; Auburn University, AL; the University of Nevada at

Las Vegas, NV; and the University of Colorado at Colorado Springs, CO. He has

authored more than 100 research papers. He has also authored one book, Compact

Models for Integrated Circuit Design: Conventional Transistors and Beyond (CRC

Press, 2015); one book chapter on Technology Computer-Aided Design (TCAD),

Introduction to Technology Computer-Aided Design, in Technology Computer

Aided Design: Simulation for VLSI MOSFET (C.K. Sarkar, ed., CRC Press, 2013);

and holds 12 US patents. His research interests include nanoscale device and process

architecture, TCAD, compact modeling, devices for renewable energy, and TCAD

and R&D management.

Dr. Saha served as the 20162017 President of the Institute of Electrical and

Electronics Engineers (IEEE) Electron Devices Society (EDS) and is currently serving

as the Senior Past President of EDS, J.J. Ebers Award Committee Chair, and

EDS Fellow Evaluation Committee Chair. He is a Fellow of IEEE and a Fellow

of the Institution of Engineering and Technology (IET, UK), and a Distinguished

Lecturer of IEEE EDS. Previously, he has served as the Junior Past President of EDS;

EDS Awards Chair; EDS Fellow Evaluation Committee Member; EDS President-

Elect; Vice President of EDS Publications; an elected member of the EDS Board of

Governors; Editor-In-Chief of IEEE QuestEDS; Chair of EDS George Smith and Paul

Rappaport Awards; Editor of Region 5&6 EDS Newsletter; Chair of EDS Compact

Modeling Technical Committee; Chair of EDS North America West Subcommittee

for Regions/Chapters; a member of the IEEE Conference Publications Committee;

a member of the IEEE TAB Periodicals Committee; and the Treasurer, Vice Chair,

and Chair of the Santa Clara Valley-San Francisco EDS chapter.

Dr. Saha served as the head guest editor for the IEEE Transactions on

Electron Devices (T-ED) Special Issues (SIs) on Advanced Compact Models and

45-nm Modeling Challenges and Compact Interconnect Models for Giga Scale

Integration; and as a guest editor for the T-ED SI on Advanced Modeling of Power

Devices and their Applications and the IEEE Journal of Electron Devices

Society (J-EDS) SI on Flexible Electronics from the Selected Extended Papers at

2018 IFETC. He has also served as a member of the editorial board of the World

Journal of Condensed Matter Physics (WJCMP), published by the Scientific

Research Publishing (SCIRP).
Lisainfo e-raamatute kohta Lisainfo e-raamatute kohta
Püsilink: https://www.kriso.ee/db/97804299980962e.html
Märksõnad: