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E-raamat: Fundamentals of Tunnel Field-Effect Transistors

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, (Indraprastha Institute of Information Technology, DELHI, INDIA)
  • Formaat: 306 pages
  • Ilmumisaeg: 26-Oct-2016
  • Kirjastus: CRC Press Inc
  • Keel: eng
  • ISBN-13: 9781498767163
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Fundamentals of Tunnel Field-Effect TransistorsSuurem pilt
  • Formaat: 306 pages
  • Ilmumisaeg: 26-Oct-2016
  • Kirjastus: CRC Press Inc
  • Keel: eng
  • ISBN-13: 9781498767163
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"During the last decade, there has been a great deal of interest in TFETs. To the best authors' knowledge, no book on TFETs currently exists. The proposed book provides readers with fundamental understanding of the TFETs. It explains the interesting characteristics of the TFETs, pointing to their strengths and weaknesses, and describes the novel techniques that can be employed to overcome these weaknesses and improve their characteristics. Different tradeoffs that can be made in designing TFETs have alsobeen highlighted. Further, the book provides simulation example files of TFETs that could be run using a commercial device simulator"--

During the last decade, there has been a great deal of interest in TFETs. To the best authors’ knowledge, no book on TFETs currently exists. The proposed book provides readers with fundamental understanding of the TFETs. It explains the interesting characteristics of the TFETs, pointing to their strengths and weaknesses, and describes the novel techniques that can be employed to overcome these weaknesses and improve their characteristics. Different tradeoffs that can be made in designing TFETs have also been highlighted. Further, the book provides simulation example files of TFETs that could be run using a commercial device simulator.

Preface xiii
1 CMOS Scaling
1(26)
1.1 Introduction
1(1)
1.2 Basics of MOSFET and CMOS
2(9)
1.2.1 MOSFET Structure and Operation
3(3)
1.2.2 Operation of MOSFET as a Switch
6(3)
1.2.3 Short-Channel Effects in a MOSFET
9(1)
1.2.4 CMOS Inverter
9(1)
1.2.5 Power Dissipation in a CMOS Circuit
10(1)
1.3 CMOS Scaling
11(1)
1.4 Types of CMOS Scaling
12(2)
1.4.1 Constant-Field Scaling
13(1)
1.4.2 Constant-Voltage Scaling
13(1)
1.5 Historical Perspective of CMOS Scaling
14(3)
1.6 Current Trends in CMOS Scaling
17(3)
1.7 Challenges in Continued CMOS Scaling
20(1)
1.8 Emerging Research Devices
21(1)
1.9 Summary
22(5)
2 Quantum Tunneling
27(18)
2.1 Introduction
27(1)
2.2 Quantum Mechanics
27(2)
2.3 Quantum Mechanical Tunneling
29(4)
2.4 Solving the Tunneling Problem
33(4)
2.4.1 Analytic Approximation Methods
33(3)
2.4.2 Numerical Methods
36(1)
2.5 Junction Breakdown Due to Tunneling
37(2)
2.6 Tunnel Diode
39(2)
2.7 Summary
41(4)
3 Basics of Tunnel Field-Effect Transistors
45(38)
3.1 Introduction
45(1)
3.2 Device Structure
45(4)
3.3 Operation
49(3)
3.4 Transfer Characteristics
52(3)
3.4.1 OFF-State
52(2)
3.4.2 Subthreshold Region
54(1)
3.4.3 Super-Threshold Region
55(1)
3.5 Subthreshold Swing
55(5)
3.6 Tunneling Current
60(4)
3.7 Output Characteristics
64(3)
3.7.1 Tunnel Resistance-Dominated Region
65(1)
3.7.2 Channel Resistance-Dominated Region
65(1)
3.7.3 Saturation Region
66(1)
3.8 Threshold Voltage
67(1)
3.9 Different Types of TFETs
68(1)
3.10 Impact of Device Parameters
69(2)
3.10.1 Gate Dielectric
69(1)
3.10.2 Body Thickness
69(1)
3.10.3 Source Doping Concentration and Profile
70(1)
3.10.4 Channel Length
70(1)
3.11 Ambipolar Current
71(3)
3.12 Impact of Temperature
74(1)
3.13 Promises and Limitations
75(1)
3.14 Summary
76(7)
4 Boosting ON-Current in Tunnel Field-Effect Transistor
83(40)
4.1 Introduction
83(1)
4.2 Types of Techniques to Boost ON-Current
83(2)
4.3 Gate Engineering
85(6)
4.3.1 Thickness and Dielectric Constant of Gate Oxide
85(1)
4.3.2 Multiple Gates
86(1)
4.3.3 Spacer Engineering
86(2)
4.3.4 Asymmetric Gate Structures
88(2)
4.3.5 Quality of Gate Oxide
90(1)
4.4 Tunneling Junction Engineering
91(7)
4.4.1 Source Doping
91(2)
4.4.2 Tunneling Area
93(2)
4.4.3 Heterojunctions
95(3)
4.5 Materials Engineering
98(10)
4.5.1 Germanium
99(1)
4.5.2 III-V Semiconductors
99(3)
4.5.3 Carbon
102(4)
4.5.4 Nanowires
106(2)
4.6 Strain Engineering
108(2)
4.7 Summary
110(13)
5 III-V Tunnel Field-Effect Transistor
123(32)
5.1 Introduction
123(1)
5.2 III-V Semiconductors
124(3)
5.3 Challenges in III-V Materials-Based MOSFETs
127(3)
5.4 A III-V TFET Prototype
130(3)
5.5 Heterojunction III-V TFETs
133(3)
5.6 Device Optimization in III-V TFETs
136(2)
5.7 Gate Dielectric in III-V TFETs
138(2)
5.7.1 Processing Techniques
139(1)
5.7.2 Interface Material Engineering
140(1)
5.7.3 Hybrid III-V/Silicon TFET
140(1)
5.8 Tunneling Junction
140(3)
5.9 Impact of Temperature
143(1)
5.10 Challenges in p-Type III-V TFETs
144(1)
5.11 Current State and Future Perspective
145(1)
5.12 Summary
146(9)
6 Carbon-Based Tunnel Field-Effect Transistor
155(30)
6.1 Introduction
155(1)
6.2 Carbon Nanotubes (CNTs)
156(2)
6.3 CNT TFETs
158(3)
6.3.1 Ballistic Transport
160(1)
6.3.2 Quantum Capacitance
160(1)
6.4 Device Optimization of CNT TFETs
161(2)
6.5 Challenges and Future Perspectives of CNT TFETs
163(2)
6.6 Graphene
165(4)
6.7 Graphene TFETs
169(6)
6.7.1 GNR-Based TFET
170(2)
6.7.2 Bilayer-Graphene TFET
172(1)
6.7.3 Graphene-on-SiC-Based TFET
173(1)
6.7.4 Zero-Bandgap Graphene TFET
174(1)
6.8 Device Optimization of Graphene TFETs
175(3)
6.9 Challenges and Future of Graphene TFETs
178(1)
6.10 Summary
178(7)
7 Nanowire Tunnel Field-Effect Transistor
185(22)
7.1 Introduction
185(1)
7.2 Basics of Nanowires
185(6)
7.3 Silicon Nanowire TFETs
191(4)
7.4 Nanowire Heterostructure-Based TFETs
195(5)
7.4.1 Ge--SixGe21-x Core-Shell NWTFET
195(1)
7.4.2 InAs-Si Heterostructure NWTFET
196(2)
7.4.3 InGaAs-Si Heterostructure NWTFET
198(1)
7.4.4 InAs-SiGe Heterostructure NWTFET
198(1)
7.4.5 GaSb/InAs Heterostructure NWTFET
198(2)
7.5 Device Optimization of Nanowire TFETs
200(1)
7.6 Challenges and Future of Nanowire TFETs
200(1)
7.7 Summary
201(6)
8 Models for Tunnel Field-Effect Transistor
207(22)
8.1 Introduction
207(1)
8.2 Tunneling Models
208(3)
8.2.1 Local Tunneling Models
208(1)
8.2.2 Non-Local Tunneling Models
209(2)
8.3 Simulation of TFETs
211(2)
8.3.1 Semi-Classical Simulation
211(1)
8.3.2 Full Quantum Simulation
212(1)
8.4 Types of TFET Models
213(4)
8.4.1 Lookup Table (LUT)-Based Models
213(1)
8.4.2 Empirical and Semi-Empirical Models
214(1)
8.4.3 Analytical Models
215(2)
8.5 Drain Current Model
217(5)
8.6 Summary
222(7)
9 Applications of Tunnel Field-Effect Transistors
229(32)
9.1 Introduction
229(1)
9.2 Electrical Characteristics of TFETs
230(5)
9.2.1 Steep Subthreshold Swing
230(1)
9.2.2 Unidirectional Conduction
230(2)
9.2.3 Onset of Current in the Output Characteristics
232(1)
9.2.4 Gate-to-Drain Miller Capacitance
233(1)
9.2.5 Matching Characteristics of NMOS-Type TFETs and PMOS-Type TFETs
233(1)
9.2.6 Other Electrical Characteristics
234(1)
9.3 Digital Circuits
235(8)
9.3.1 TFET Inverters
235(5)
9.3.2 Applications in Digital Circuits
240(3)
9.4 Applications in Memories
243(4)
9.5 Analog Circuits
247(4)
9.5.1 Intrinsic Analog Parameters of TFETs
247(3)
9.5.2 Applications in Analog Circuits
250(1)
9.6 Future Perspective of TFETs in Circuits
251(1)
9.7 Summary
252(9)
10 Future Perspectives
261(14)
10.1 Introduction
261(1)
10.2 State-of-the-Art TFETs
261(2)
10.3 Comparison with MOSFET
263(1)
10.4 Other Low-Subthreshold Swing Devices
264(4)
10.4.1 Impact-Ionization MOS (IMOS)
265(1)
10.4.2 Nanoelectromechanical Switch (NEMS)
266(1)
10.4.3 Negative Capacitance FETs (NCFETs)
267(1)
10.5 Challenges and the Road Ahead
268(1)
10.6 Summary
269(6)
Appendix A Simulation of Double Gate Tunnel Field-Effect Transistor
275(6)
A.1 Device Structure
275(2)
A.2 Sample Input File
277(4)
Appendix B Simulation of SOI Tunnel Field-Effect Transistor
281(6)
B.1 Device Structure
281(2)
B.2 Sample Input File
283(4)
Index 287
Sneh Saurabh, Mamidala Jagadesh Kumar
Lisainfo e-raamatute kohta Lisainfo e-raamatute kohta
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