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E-raamat: Guidebook for Managing Silicon Chip Reliability

, , (University of Maryland, College Park, USA University of Maryland, College Park, USA)
  • Formaat: 224 pages
  • Ilmumisaeg: 22-Nov-2017
  • Kirjastus: CRC Press Inc
  • ISBN-13: 9781351443562
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  • Formaat: 224 pages
  • Ilmumisaeg: 22-Nov-2017
  • Kirjastus: CRC Press Inc
  • ISBN-13: 9781351443562
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Achieving cost-effective performance over time requires an organized, disciplined, and time-phased approach to product design, development, qualification, manufacture, and in-service management. Guidebook for Managing Silicon Chip Reliability examines the principal failure mechanisms associated with modern integrated circuits and describes common practices used to resolve them.

This quick reference on semiconductor reliability addresses the key question: How will the understanding of failure mechanisms affect the future?

Chapters discuss:
  • failure sites, operational loads, and failure mechanism
  • intrinsic device sensitivities
  • electromigration
  • hot carrier aging
  • time dependent dielectric breakdown
  • mechanical stress induced migration
  • alpha particle sensitivity
  • electrostatic discharge (ESD) and electrical overstress
  • latch-up
  • qualification
  • screening
  • guidelines for designing reliability

    Guidebook for Managing Silicon Chip Reliability focuses on device failure and causes throughout - providing a thorough framework on how to model the mechanism, test for defects, and avoid and manage damage. It will serve as an exceptional resource for electrical engineers as well as mechanical engineers working in the field of electronic packaging.
  • 1. INTRODUCTION
    1(2)
    2. HOW DEVICES FAIL
    3(4)
    2.1 Intrinsic Mechanisms
    5(1)
    2.2 Extrinsic Mechanisms
    5(2)
    3. INTRINSIC DEVICE SENSITIVITIES
    7(6)
    3.1 Device Transconductance Sensitivities
    7(1)
    3.2 Leakage Current Sensitivities
    8(1)
    3.3 Breakdown Issues
    9(4)
    4. ELECTROMIGRATION
    13(6)
    4.1 Description of the Mechanism
    13(2)
    4.2 Modeling of the Mechanism
    15(1)
    4.3 How to Detect/Test
    16(1)
    4.4 How to Manage
    17(2)
    5. HOT CARRIER AGING
    19(6)
    5.1 Description of the Mechanism
    19(2)
    5.2 Modeling of the Mechanism
    21(1)
    5.3 Detection of Hot Carrier Aging
    21(1)
    5.4 Avoidance of Hot Carrier Aging
    22(3)
    6. TIME-DEPENDENT DIELECTRIC BREAKDOWN
    25(6)
    6.1 Description of the Mechanism
    25(3)
    6.2 Modeling of the Mechanism
    28(1)
    6.3 How to Detect/Test
    29(1)
    6.4 How to Avoid and Manage
    29(2)
    7. MECHANICAL STRESS-INDUCED MIGRATION
    31(6)
    7.1 Description of the Mechanism
    31(1)
    7.2 Modeling of the Mechanism
    32(2)
    7.3 How to Detect/Test
    34(1)
    7.4 How to Manage
    35(2)
    8. ALPHA PARTICLE SENSITIVITY
    37(4)
    8.1 Description of the Mechanism
    37(1)
    8.2 Modeling of the Mechanism
    38(1)
    8.3 Prevention of Alpha Particle-Induced Damage
    39(2)
    9. ELECTROSTATIC DISCHARGE AND ELECTRICAL OVERSTRESS
    41(4)
    9.1 Description of the Mechanisms
    41(1)
    9.2 Modeling of the Mechanism
    42(1)
    9.3 Avoiding ESD/EOS Failures
    43(2)
    10. LATCHUP
    45(4)
    10.1 Description of the Mechanism
    45(2)
    10.2 How to Detect
    47(1)
    10.3 How to Avoid
    47(2)
    11. DESIGN FOR RELIABILITY
    49(12)
    11.1 Design System
    51(3)
    11.2 Effective Management of Wearout Failures
    54(2)
    11.3 Extrinsic Reliability Mechanisms
    56(1)
    11.4 Infant Mortality Failure Mechanisms
    57(1)
    11.5 Circuit Sensitivities
    58(3)
    12. PROCESS DEVELOPMENT
    61(58)
    12.1 Introduction
    61(1)
    12.2 Multilevel Interconnect System
    61(2)
    12.3 Multilevel Interconnect Flow
    63(1)
    12.4 Dielectric Deposition
    63(16)
    12.5 Dielectric Planarization
    79(14)
    12.6 Contact/Via Formation
    93(9)
    12.7 Metals
    102(15)
    12.8 Summary
    117(2)
    13. MANUFACTURING
    119(54)
    13.1 Introduction
    119(1)
    13.2 Manufacturing Challenges
    119(15)
    13.3 Process Integration
    134(2)
    13.4 Yield Analysis
    136(18)
    13.5 Defect Reduction
    154(18)
    13.6 Summary
    172(1)
    14. QUALIFICATION
    173(10)
    14.1 Qualification and Reliability Monitoring Testing
    173(4)
    14.2 Virtual Qualification
    177(6)
    15. SCREENING
    183(12)
    15.1 Functional Tests
    183(1)
    15.2 Burn-In Tests
    184(10)
    15.3 IDDQ Tests
    194(1)
    16. SUMMARY
    195(4)
    17. REFERENCES
    199(14)
    18. INDEX
    213


    Pecht, Michael; Radojcic, Riko; Rao, Gopal