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E-raamat: Harnessing VLSI System Design with EDA Tools

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  • Formaat: PDF+DRM
  • Ilmumisaeg: 03-Oct-2011
  • Kirjastus: Springer
  • Keel: eng
  • ISBN-13: 9789400718647
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Harnessing VLSI System Design with EDA ToolsSuurem pilt
  • Formaat: PDF+DRM
  • Ilmumisaeg: 03-Oct-2011
  • Kirjastus: Springer
  • Keel: eng
  • ISBN-13: 9789400718647
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In this book the authors synergize VHDL programming with appropriate EDA tools to present a foolproof design system. Along with the VHDL coding issues, the simulation and synthesis with the various toolsets enables the reader to visualize the final design.



With the proliferation of VHDL, the reference material also grew in the same order. Today there is good amount of scholarly literature including many books describing various aspects of VHDL. However, an indepth review of these books reveals a different story. Many of them have emerged simply as an improved version of the manual. While some of them deal with the system design issues, they lack appropriate exemplifying to illustrate the concepts. Others give large number of examples, but lack the VLSI system design issues.

In nutshell, the fact which gone unnoticed by most of the books, is the growth of the VLSI is not merely due to the language itself, but more due to the development of large number of third party tools useful from the FPGA or semicustom ASIC realization point of view. In the proposed book, the authors have synergized the VHDL programming with appropriate EDA tools so as to present a full proof system design to the readers. In this book along with the VHDL coding issues, the simulation and synthesis with the various toolsets enables the potential reader to visualize the final design. The VHDL design codes have been synthesized using different third party tools such as Xilinx Web pack Ver.11, Modelsim PE, Leonrado Spectrum and Synplify Pro. Mixed flow illustrated by using the above mentioned tools presents an insight to optimize the design with reference to the spatial, temporal and power metrics.

1 Introduction
1(14)
1.1 Introduction
1(1)
1.2 Prologue
1(1)
1.3 EDA: From Methodologies, Algorithms, Tools to Integrated Circuits and Systems
2(2)
1.4 EDA from Halcyon's Days to the Blooming Paradigm of Chip Industry
4(1)
1.5 Categories of the EDA Tools
5(1)
1.6 Quo Vadis, EDA? The Challenges and Opportunities
6(2)
1.7 Just One More Book on EDA or Value Addition to the Scholarly Literature by US?
8(1)
1.8 Designing the System as SoC Using the Soft IP Cores
9(1)
1.9 Types of IP Cores
10(1)
1.10 Design Issues Pertaining to the Soft IP Cores
11(1)
1.11 Justifying FPGA as the Prototyping Platform
11(3)
1.12 Justifying the Differing Flavors of Languages Used in This Book
14(1)
2 Development of FPGA Based Network on Chip for Circumventing Spam
15(36)
2.1 Introduction
15(1)
2.2 Conception of the Spam Mail
16(2)
2.3 FPGA Based Network on Chip for Circumventing Spam
18(3)
2.3.1 Inspiration
18(1)
2.3.2 Core Concept
18(1)
2.3.3 Method
18(1)
2.3.4 Motivation
19(1)
2.3.5 Advantages of FPGA Based Antispam Appliance in Nutshell
19(1)
2.3.6 Significance of the Work
20(1)
2.4 Tools Infrastructure and Design Flow
21(2)
2.4.1 Handel C
21(1)
2.4.2 ISE Webpack 9.2
22(1)
2.4.3 EDK Version 9.2
22(1)
2.4.4 Xilinx Starter Kit
23(1)
2.5 Introducing Hardware-Software Co-design
23(1)
2.6 Hardware Software Co-design
24(4)
2.6.1 Motivation for Hw/Sw Co-design
25(1)
2.6.2 Advantages of Hw/Sw Co-design Methodology
26(1)
2.6.3 State of the Art Hw-Sw Co-design Methodologies
26(2)
2.7 Hardware-Software Codesign Framework Proposed in the Present Case Study
28(2)
2.7.1 Addressing the Issues Through Co-design
29(1)
2.8 Description of System at Higher Level
30(1)
2.9 Resolving the System a Step Down
30(1)
2.10 System Design
31(8)
2.10.1 Microblaze Processor
33(1)
2.10.2 PLB BUS
33(2)
2.10.3 XPS UART Lite
35(1)
2.10.4 Off Chip Level Converter
35(1)
2.10.5 XPS Ethernet Lite
35(1)
2.10.6 SMSC LAN83C185 High Performance Single Chip Low Power 10/100 Mbps Ethernet Physical Layer Transceiver (PHY)
36(1)
2.10.7 XPS Timer
36(1)
2.10.8 XPS Interrupt Controller
37(1)
2.10.9 Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller
37(2)
2.10.10 Off Chip DDR SDRAM MT46V32M16
39(1)
2.11 Development of Soft IP Core of Bloom Filter
39(6)
2.11.1 Justifying Bloom Filters for the Keyword Parsing
39(1)
2.11.2 Theoretical Foundations of Bloom Filter
40(1)
2.11.3 Hash Function
40(2)
2.11.4 Deciding the Size and Number of Hash Functions in Our Bloom Filter Implementation
42(3)
2.12 Presenting System Design of Purely Software Modules
45(2)
2.13 Integrating of the Hardware-Software Modules Using EDK
47(1)
2.14 Setting the POP3 Client and Describing Overall Working of the System
47(2)
2.15 Conclusion
49(2)
3 Analog Front End and FPGA Based Soft IP Core for ECG Logger
51(42)
3.1 Prior Art
51(2)
3.2 The Very Rationale of the System
53(1)
3.3 Analog Front End of the Setup
54(11)
3.3.1 Leads Formation
54(1)
3.3.2 Restricting Number of Leads
54(2)
3.3.3 ECG Instrumentation Amplifier
56(1)
3.3.4 Deriving the Signal from the Augmented Leads
56(4)
3.3.5 Filtering the ECG Signal
60(2)
3.3.6 Multiplexing the Lead Signals
62(1)
3.3.7 Post-multiplexer Amplifier Stage
62(1)
3.3.8 Digitization of the ECG Signal
62(1)
3.3.9 FPGA Based Handshake Micro-logic
63(1)
3.3.10 MODEM Interface
63(2)
3.4 VHDL Implementation of the ECG Soft IP Core
65(6)
3.4.1 Driving ADC: LTC 1407 and Storing Data in 3D RAM
65(4)
3.4.2 Details of the VHDL Code
69(1)
3.4.3 VHDL Processes for Conversion and Storage in 3D Memory: (Process P_conv, P_SHIFT and P_STORE)
69(2)
3.4.4 VHDL Process for Serial Transmission of the ECG Signal (Process Serial)
71(1)
3.5 Modelsim Simulation Results
71(2)
3.6 Synthesis Results Using Mentor Graphics Tool: Leonardo Spectrum
73(3)
3.6.1 Synthesis Report
73(3)
3.6.2 RTL View
76(1)
3.6.3 Technology Schematic View
76(1)
3.6.4 Critical Path Schematic
76(1)
3.7 Monitoring the ECG Using MODEM Based Setup
76(1)
3.7.1 Tele-monitoring of the ECG Signal at the Hospital End
76(1)
3.8 ECG Signal Reconstruction Mechanism at the Hospital End
76(5)
3.8.1 DAC Interfacing Details
78(1)
3.8.2 FPGA Driving Demultiplexer and DAC: Core Algorithm
79(2)
3.8.3 Serial ECG Receiver: Flow Chart
81(1)
3.9 VHDL Listing for Driving the Analog Demultiplexer and Serial DAC from Spartan-3E FPGA
81(2)
3.10 Discussion Regarding the VHDL Implementation
83(1)
3.10.1 Process Serial_P
83(1)
3.10.2 Process S_OUT
84(1)
3.11 Modelsim Simulation Results
84(1)
3.12 Synthesis Results Using Mentor Graphics Tool: Leonardo Spectrum
85(5)
3.12.1 Synthesis Report
85(1)
3.12.2 RTL View
86(4)
3.12.3 Technology Schematic View
90(1)
3.12.4 Critical Path Schematic
90(1)
3.13 Conclusion
90(3)
4 FPGA Based Multifunction Interface for Embedded Applications
93(34)
4.1 Introduction
93(1)
4.2 Universal FPGA Based Interface for High End Embedded Applications
94(1)
4.2.1 Hardware Aspects
94(1)
4.3 Soft IP Core for the LCD Interface
95(5)
4.4 Soft IP Core for the DAC Interface
100(1)
4.5 Handel C Listing of the Soft IP Core for the DAC Interface
101(5)
4.6 Soft IP Core for the Linear Tech LTC6912-1 Dual Amp Interface
106(2)
4.7 Soft IP Core for the ADC Interface
108(5)
4.8 Soft IP Core for the VGA Interface
113(4)
4.9 Soft IP Core for the Keyboard Interface
117(5)
4.10 Triangular Wave Generator Using DAC
122(4)
4.11 Conclusion
126(1)
5 FPGA Based High Resolution Time to Digital Converter
127(20)
5.1 Introduction
127(1)
5.2 TDC: Prior Art
128(1)
5.3 TDC Using Vernier Principle
129(8)
5.3.1 Coarse measurement
130(3)
5.3.2 Fine Measurement
133(4)
5.4 Simulation and Verilog Modules
137(9)
5.4.1 Ring Oscillator (Fast Clock) RTL Schematic
139(1)
5.4.2 Verilog Module for Ring Oscillator (Fast Clock)
139(1)
5.4.3 Verilog Module for Ring Oscillator (Slow Clock)
140(2)
5.4.4 Phase Detector
142(1)
5.4.5 Simulation Wave Form of Phase Detector
142(1)
5.4.6 Verilog Module for 8 Bit Counter
142(1)
5.4.7 RTL Schematic of 8 Bit Counter
143(1)
5.4.8 Simulation Results of 8 Bit Counter
143(1)
5.4.9 Verilog Module for 8 Bit Counter
144(1)
5.4.10 RTL Schematic of Time to Digital Converter
144(1)
5.4.11 Schematic of Time to Digital Converter
145(1)
5.4.12 Verilog Module for Time to Digital Converter
145(1)
5.5 Applications of the TDC Implemented
146(1)
References 147
This book explores various dimensions of EDA technologies for achieving different goals in VLSI system design.  Although the scope of EDA is very broad and comprises diversified hardware and software tools to accomplish different phases of VLSI system design, such as design, layout, simulation, testability, prototyping and implementation, this book focuses only on demystifying the code, a.k.a. firmware development and its implementation with FPGAs.  Since there are a variety of languages for system design, this book covers various issues related to VHDL, Verilog and System C synergized with EDA tools, using a variety of case studies such as testability, verification and power consumption.





Covers aspects of VHDL, Verilog and Handel C in one text; Enables designers to judge the appropriateness of each EDA tool for relevant applications; Omits discussion of design platforms and focuses on design case studies; Uses design case studies from diversified application domains such as network on chip, hospital on chip, analog to digital conversion and embedded system design; Facilitates with code and tool flows the design cycle for systems on chip with increasing complexity; Demonstrates standard development cycles, making use of latest concepts such as Soft IP Cores, Hardware Software Codesign etc.
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