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E-raamat: High Performance ASIC Design: Using Synthesizable Domino Logic in an ASIC Flow

  • Formaat: PDF+DRM
  • Ilmumisaeg: 21-Aug-2008
  • Kirjastus: Cambridge University Press
  • Keel: eng
  • ISBN-13: 9780511451294
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  • Formaat: PDF+DRM
  • Ilmumisaeg: 21-Aug-2008
  • Kirjastus: Cambridge University Press
  • Keel: eng
  • ISBN-13: 9780511451294
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A methodology for using domino logic in an ASIC design flow for graduate students, researchers, and circuit designers in industry.

Presenting a methodology for using domino logic in an ASIC design flow developed over several years in an industrial context, this text covers practical issues related to the use of domino logic in an automated framework, and brings together all the knowledge needed to apply these design techniques in practice. Beginning with a discussion of how to achieve high speed in ASIC designs, subsequent chapters detail the design and characterization of standard cell compatible domino logic libraries and an advanced domino logic synthesis flow. The results achieved by using automated domino logic design techniques, including silicon measurements, are used to validate the presented solution. With design examples including the implementation of the execution unit of a microprocessor and a Viterbi decoder, this text is ideal for graduate students and researchers in electrical and computer engineering and also for circuit designers in industry.

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A methodology for using domino logic in an ASIC design flow for graduate students, researchers, and circuit designers in industry.
Preface vii
Abbreviations ix
An introduction to domino logic
1(17)
CMOS and NMOS
1(4)
Domino logic circuits
5(7)
Clocking domino logic
12(3)
Summary
15(3)
High-speed digital design
18(19)
Microprocessors since 1989
18(4)
Microarchitectures for high speed
22(9)
Designing and using high-speed memories
31(4)
What to remember if applying domino logic
35(2)
Domino logic library design
37(33)
High-speed digital circuit design
37(5)
An introduction to standard cells
42(3)
Designing a high-performance standard cell library
45(3)
Circuit design of domino logic cells: a qualitative approach
48(3)
Circuit design of domino logic cells: a quantitative approach
51(12)
Characterizing domino logic-compatible registers
63(2)
Layout of domino logic standard cells
65(1)
Timing models for domino logic cells
66(4)
Domino logic synthesis
70(38)
Introduction to domino logic synthesis
70(3)
Unate transform
73(2)
Phase assignment
75(2)
Phase-assignment rules
77(9)
An example domino synthesis flow
86(20)
Schematic capture of domino designs
106(2)
Circuits designed with domino logic in an ASIC flow
108(19)
Introduction
108(1)
Domino integer execution unit
108(11)
A synthesized domino logic DSP core
119(2)
A synthesizable domino logic Viterbi add-compare-select (ACS) test chip
121(3)
Intel's published domino logic synthesis flow
124(2)
Conclusions
126(1)
Evolution of domino logic synthesis
127(16)
The state of digital ASIC design methodologies
127(1)
Process trends and domino logic
128(2)
Clocking methodology for domino circuits
130(2)
Synthesizing other dynamic logic families
132(5)
Flow improvements for domino synthesis
137(4)
The case for domino logic synthesis
141(2)
Index 143
Razak Hossain is Senior Principal Engineer at STMicroelectonics, San Diego, California, where he has worked since 2000 on high speed ASIC chips and design methodologies. He gained his Ph.D. in Electrical Engineering from the University of Rochester, New York, in 1995, before taking a position at Mentor Graphics Corporation, Warren, New Jersey.