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E-raamat: High Performance Integer Arithmetic Circuit Design on FPGA: Architecture, Implementation and Design Automation

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High Performance Integer Arithmetic Circuit Design on FPGA: Architecture, Implementation and Design AutomationSuurem pilt
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This book describes the optimized implementations of several arithmetic datapath, controlpath and pseudorandom sequence generator circuits for realization of high performance arithmetic circuits targeted towards a specific family of the high-end Field Programmable Gate Arrays (FPGAs). It explores regular, modular, cascadable and bit-sliced architectures of these circuits, by directly instantiating the target FPGA-specific primitives in the HDL. Every proposed architecture is justified with detailed mathematical analyses. Simultaneously, constrained placement of the circuit building blocks is performed, by placing the logically related hardware primitives in close proximity to one another by supplying relevant placement constraints in the Xilinx proprietary “User Constraints File”. The book covers the implementation of a GUI-based CAD tool named FlexiCore integrated with the Xilinx Integrated Software Environment (ISE) for design automation of platform-specific high-performance arithmetic circuits from user-level specifications. This tool has been used to implement the proposed circuits, as well as hardware implementations of integer arithmetic algorithms where several of the proposed circuits are used as building blocks. Implementation results demonstrate higher performance and superior operand-width scalability for the proposed circuits, with respect to implementations derived through other existing approaches. This book will prove useful to researchers, students and professionals engaged in the domain of FPGA circuit optimization and implementation.
1 Introduction
1(10)
1.1 Background of FPGA-Based Design
1(1)
1.2 Limitations of FPGA CAD Tools
2(1)
1.3 Overview of Design Philosophy for FPGAs
3(1)
1.3.1 Target FPGA-Specific Hardware Primitive Instantiation
3(1)
1.4 Existing FPGA CAD Tools
4(2)
1.4.1 Xilinx IP Core Generator
4(1)
1.4.2 FloPoCo (Floating-Point Cores)
5(1)
1.5 Recent Works on High Performance Circuit Realization on Xilinx FPGAs
6(1)
1.6 Major Contributions of the Book
6(2)
1.7 Organization of the Book
8(1)
1.8 Summary
9(2)
References
9(2)
2 Architecture of Target FPGA Platform
11(8)
2.1 Introduction
11(1)
2.2 Fabric Slice Architecture for Virtex-5 FPGAs
12(2)
2.3 Fabric Slice Architecture for Virtex-6 FPGAs
14(1)
2.4 DSP Slice Architecture for Virtex-5 and Virtex-6 FPGAs
15(1)
2.5 Implementation Overview
16(1)
2.6 Summary
17(2)
References
17(2)
3 A Fabric Component Based Design Approach for High-Performance Integer Arithmetic Circuits
19(12)
3.1 Introduction
19(1)
3.2 Existing Work
20(1)
3.3 Guidelines for High-Performance Realization
21(7)
3.4 Summary
28(3)
References
28(3)
4 Architecture of Datapath Circuits
31(42)
4.1 Introduction
31(1)
4.2 Integer Adder/Subtractor Architecture
32(11)
4.2.1 Hybrid Ripple Carry Adder (Hybrid RCA)
32(2)
4.2.2 Xilinx DSP Slice-Based Adder
34(1)
4.2.3 FloPoCo-Based Adder
35(1)
4.2.4 Fast Carry Adder Using Carry-Lookahead Mechanism
35(4)
4.2.5 Adder Implementation Results
39(4)
4.3 Absolute Difference Circuit Architecture
43(5)
4.3.1 Proposed Absolute Difference Circuit
43(1)
4.3.2 DSP Slice-Based Absolute Difference Circuit
44(1)
4.3.3 FloPoCo-Based Absolute Difference Circuit
45(1)
4.3.4 Absolute Difference Circuit Implementation Results
46(2)
4.4 Integer Multiplier Architecture
48(9)
4.4.1 Unsigned Integer Multiplier
48(1)
4.4.2 Two's Complement Multiplier
49(2)
4.4.3 Combined Unsigned and Two's Complement Multiplier
51(4)
4.4.4 DSP Slice-Based Signed Multiplier
55(1)
4.4.5 FloPoCo-Based Signed Multiplier
55(1)
4.4.6 Multiplier Implementation Results
55(2)
4.5 Integer Squarer Architecture
57(10)
4.5.1 Unsigned Squarers
59(1)
4.5.2 Two's Complement Squarers
60(4)
4.5.3 Combined Unsigned and Two's Complement Squarer
64(1)
4.5.4 DSP Slice-Based Squarers
65(2)
4.5.5 FloPoCo-Based Squarers
67(1)
4.5.6 Squarer Implementation Results
67(1)
4.6 Universal Shift Register Architecture
67(3)
4.6.1 Universal Shift Register
67(2)
4.6.2 Universal Shift Register Implementation Results
69(1)
4.7 Summary
70(3)
References
71(2)
5 Architecture of Controlpath Circuits
73(12)
5.1 Introduction
73(1)
5.2 Integer Comparator Architecture
73(6)
5.2.1 Proposed Comparator Architecture
73(3)
5.2.2 DSP Slice-Based Comparator
76(1)
5.2.3 Comparator Implementation Results
77(2)
5.3 Loadable Bidirectional Binary Counter Architecture
79(3)
5.3.1 Proposed Counter Architecture
79(2)
5.3.2 DSP Slice-Based Counter
81(1)
5.3.3 Counter Implementation Results
81(1)
5.4 Summary
82(3)
References
83(2)
6 Compact FPGA Implementation of Linear Cellular Automata
85(8)
6.1 Introduction
85(1)
6.2 Preliminaries on Cellular Automata
86(2)
6.3 Adapting CA to the Native FPGA Architecture
88(1)
6.4 CA Implementation Results
89(1)
6.5 Summary
90(3)
References
91(2)
7 Design Automation and Case Studies
93(16)
7.1 Introduction
93(1)
7.2 The FlexiCore CAD Tool
94(3)
7.3 Case Studies
97(9)
7.3.1 GCD Calculator Circuit
98(4)
7.3.2 Distributed Arithmetic-Based Matrix Multiplication Circuit
102(4)
7.4 Summary
106(3)
References
107(2)
8 Conclusions and Future Work
109(4)
8.1 Introduction
109(1)
8.2 Contributions of the Book
109(1)
8.3 Future Research Directions
110(3)
References
112(1)
Index 113
Ayan Palchaudhuri is a Ph.D. student in the Department of Electronics and Electrical Communication Engineering (E&ECE) of Indian Institute of Technology (IIT) Kharagpur. He has received the M.S. degree from the Department of Computer Science and Engineering (CSE), IIT Kharagpur, in 2015. He has over two-and-a-half years of work experience as a Junior Project Assistant in the Department of CSE, IIT Kharagpur. His research interests include VLSI Architecture Design and Computer Arithmetic. He is the co-author of two conference papers, one journal, one book chapter and a patent has been filed based on his research work. His research work has been recognized with the Best Poster Award in the Student Research Symposium of the 21st IEEE International Conference on High Performance Computing (HiPC) 2014.

Rajat Subhra Chakraborty is Assistant Professor in the Computer Science and Engineering Department of Indian Institute of Technology Kharagpur. He has a Ph.D. in Computer Engineering from Case Western Reserve University (Ohio, U.S.A.) and a B.E. (Hons.) in Electronics and Telecommunication Engineering from Jadavpur University (India) in 2005. He has work experience at National Semiconductor and AMD. His research interests include: Hardware Security, VLSI Design and Design Automation and Reversible Watermarking for digital content protection. He is the co-author of two published books, four book chapters and over 50 publications in international journals and conferences of repute. He is one of the recipients of the "IBM Faculty Award" for 2012, and a "Royal Academy of Engineering (U.K.) Fellowship" in 2014. He holds 1 U.S. patent, and 2 more international patents and 3 Indian patents have been filed based on his research work. Dr. Chakraborty is a member of IEEE and ACM.
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