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E-raamat: High-Speed Circuit Board Signal Integrity, Second Edition

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  • Formaat: 320 pages
  • Ilmumisaeg: 31-Jan-2017
  • Kirjastus: Artech House Publishers
  • ISBN-13: 9781630814441
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High-Speed Circuit Board Signal Integrity, Second EditionSuurem pilt
  • Formaat: 320 pages
  • Ilmumisaeg: 31-Jan-2017
  • Kirjastus: Artech House Publishers
  • ISBN-13: 9781630814441
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Stephen C. Thieraufs book offers the knowledge needed to quickly pinpoint transmission problems that can compromise the entire circuit design. Filled with on-the-job-proven examples, it demonstrates how to apply EM theory to solve signal integrity problems with a practical application-oriented approach. Discussing both design and debug issues at gigabit per second data rates, the book serves as a practical reference for projects involving high-speed serial signaling on printed wiring boards. It provides a step-by-step breakdown of the essentials of linear circuit theory, from examining practical issues of pulse propagation along lossless and lossy transmission lines to detailed guidelines for crosstalk, attenuation power supply decoupling. Other chapters include topics on the construction of etched conductors, analysis of return paths and split planes, microstrip and stripline characteristics and SMT capacitors.
Preface to the Second Edition xiii
Chapter 1 Introduction to Circuit Board Signal Integrity 1(16)
1.1 Introduction
1(1)
1.2 Pulses in the Time Domain
2(1)
1.3 Pulses in the Frequency Domain
2(6)
1.3.1 Pulse Distortion
3(1)
1.3.2 Line Spectra
4(2)
1.3.3 Upper Bandwidth
6(1)
1.3.4 How to Calculate the Spectra of Practical Pulses
7(1)
1.4 Multilayer Circuit Boards
8(3)
1.4.1 FR4 Resins
9(1)
1.4.2 Variability in Building Stack-Ups
10(1)
1.4.3 Alternate Resin Systems
10(1)
1.5 Copper Foils and Traces
11(1)
1.5.1 Surface Roughness and Resistivity
11(1)
1.5.2 High-Frequency Considerations
11(1)
1.6 Vias
12(2)
1.6.1 Anti-Functional and Nonfunctional Pads
13(1)
1.7 Surface Finishes and Solder Mask
14(1)
References
14(3)
Chapter 2 Circuit Board Resistance, Capacitance, and Inductance 17(28)
2.1 Introduction
17(1)
2.2 Resistivity and Resistance
17(3)
2.2.1 Rule of Thumb for Finding the DC Resistance of a Trace
18(1)
2.2.2 How Temperature Changes Resistance
19(1)
2.3 Understanding Capacitance and the Dielectric Constant
20(9)
2.3.1 The Dielectric Constant
21(1)
2.3.2 Determining the Capacitance Between Two Planes
22(3)
2.3.3 Finding the Capacitance of Stripline Traces
25(1)
2.3.4 Finding the Capacitance of Microstrip Traces
26(1)
2.3.5 Determining the Capacitance Present Between Traces
27(2)
2.4 Understanding Inductance and Permeability
29(4)
2.4.1 Permeability
29(1)
2.4.2 Inductance
30(1)
2.4.3 Partial Inductance
30(1)
2.4.4 Circuit Behavior of Inductance
31(1)
2.4.5 Inductive Voltage Drop
32(1)
2.5 Determining the Inductance Present Between Traces
33(9)
2.5.1 Using Mutual Inductance to Reduce Noise
34(2)
2.5.2 How Mutual Inductance Can Increase the Total Loop Inductance
36(1)
2.5.3 Finding the Inductance of a Wire Above a Return Plane
37(1)
2.5.4 Finding the Inductance of Side-by-Side Wires
38(1)
2.5.5 Finding the Inductance Between Power and Ground Planes
38(2)
2.5.6 Finding the Self-Inductance and Mutual Inductance of Microstrip
40(1)
2.5.7 Finding the Self-Inductance and Mutual Inductance of Stripline
41(1)
References
42(3)
Chapter 3 Transmission Lines 45(28)
3.1 Introduction
45(1)
3.2 Circuit Model
45(2)
3.3 Transmission-Line Impedance
47(1)
3.3.1 The Impedance of a Lossless Transmission Line
48(1)
3.4 Transmission-Line Delay and Time of Flight
48(3)
3.4.1 Delay
49(1)
3.4.2 How Delay Time Relates to Inductance and Capacitance
50(1)
3.5 Reflections and Traveling Waves
51(13)
3.5.1 Traveling Waves
52(3)
3.5.2 Reflected Waves
55(1)
3.5.3 Voltage Doubling
56(1)
3.5.4 Reflections from the Near End
56(4)
3.5.5 Multiple Reflections and Standing Waves
60(1)
3.5.6 Reflections from Capacitors and Inductors
61(2)
3.5.7 Rise Time and Frequency
63(1)
3.5.8 Transmission-Line Rule of Thumb
64(1)
3.6 Calculating Stripline Impedance
64(2)
3.7 Calculating Microstrip Impedance
66(3)
3.7.1 Impedance Equations for Bare Copper
67(1)
3.7.2 Impedance Equations for Solder Mask-Covered Copper
68(1)
3.8 Stripline Delay
69(1)
3.9 Microstrip Delay
70(1)
3.9.1 Bare Copper
70(1)
3.9.2 Adjusting for Solder Mask
70(1)
3.9.3 Important Observations
71(1)
References
71(2)
Chapter 4 Driving and Terminating Single-Ended Transmission Lines 73(22)
4.1 CMOS Output Drivers
73(2)
4.1.1 Types of Termination
74(1)
4.2 How to Select Source Series Termination Resistor Rs
75(6)
4.2.1 Estimating the Launched Voltage and Reflections
76(1)
4.3 Lowering Load Impedance with Far-End Termination
77(1)
4.3.1 Parallel Termination
78(2)
4.3.2 Thevenin Termination
80(1)
4.3.3 Connecting Rterm Directly to Vdd or Ground
80(1)
4.4 How to Terminate Point-to-Point Interconnects
81(2)
4.4.1 Fly-By Termination
82(1)
4.5 How to Terminate Transmission Lines with Multiple Loads
83(2)
4.5.1 Series Termination
84(1)
4.5.2 Far-End Parallel and Thevenin Termination
85(1)
4.6 How to Terminate Multidrop Lines
85(7)
4.6.1 Series Termination When Signal Rise Time Is Very Short
85(2)
4.6.2 Far-End Termination When Signal Rise Time Is Very Short
87(1)
4.6.3 Response When Signal Rise Time Is Comparable to the Transmission-Line Delays
87(3)
4.6.4 Branches
90(2)
References
92(3)
Chapter 5 Losses in Transmission Lines 95(40)
5.1 Introduction
95(1)
5.2 How Signals Are Affected by Loss
95(1)
5.3 How the Propagation Constant Determines Delay
96(2)
5.4 Introducing Transmission-Line Losses and the Attenuation Constant
98(4)
5.4.1 Using Decibels to Show Loss
99(2)
5.4.2 Determining Transmission-Line Loss Without the Propagation Constant
101(1)
5.5 Understanding Phase Shift, Wavelength, and Delay
102(4)
5.5.1 How the Dielectric Constant Determines Wavelength
103(1)
5.5.2 Delay
104(1)
5.5.3 Transmission-Line Delay at High and Low Frequencies
105(1)
5.6 Understanding Loop Resistance and the Skin and Proximity Effects
106(11)
5.6.1 How the Skin Effect Increases Trace Resistance
106(1)
5.6.2 Determining the Frequency Where Skin Effect Matters
107(2)
5.6.3 Introducing the Proximity Effect
109(1)
5.6.4 Two Types of Inductances: Internal and External
109(1)
5.6.5 Using the DC Resistance to Find the High-Frequency Resistance
110(1)
5.6.6 Determining the Resistance of the Return Path
111(3)
5.6.7 Why Surface Roughness Causes Resistance to Increase
114(2)
5.6.8 Differences in Conductor Losses Between Microstrips and Striplines
116(1)
5.7 How Frequency Causes Dielectric Losses to Change
117(6)
5.7.1 Understanding the Loss Tangent
118(2)
5.7.2 Calculating Circuit Board Loss Tangent and Conductance
120(1)
5.7.3 Calculating Dielectric Loss When Only the Loss Tangent Is Known
120(1)
5.7.4 Environmental Effects on Laminate Dielectric Constant and Loss Tangent
121(2)
5.8 Trade-Offs When Controlling the Total Loss Budget
123(5)
5.8.1 How to Decide to Switch to a Low-Loss Laminate
126(2)
5.9 Understanding the SPICE O, T, and W Transmission-Line Models at High Frequency
128(2)
5.10 How to Determine Stripline and Microstrip Losses Without a Field Solver
130(2)
5.10.1 Calculating Dielectric Losses
131(1)
5.10.2 Calculating Stripline Conductor Losses
131(1)
5.10.3 Calculating Microstrip Conductor Losses
131(1)
References
132(3)
Chapter 6 Understanding Trace-to-Trace Coupling and Solving Crosstalk Problems 135(26)
6.1 Introduction
135(1)
6.2 Odd and Even Modes
136(9)
6.2.1 Even Mode
136(2)
6.2.2 Odd Mode
138(1)
6.2.3 Using the Odd-Mode and Even-Mode Equations
139(3)
6.2.4 How Spacing Affects the Odd and Even Modes
142(1)
6.2.5 Stripline and Microstrip Switching Differences
143(2)
6.3 Crosstalk
145(3)
6.3.1 Coupled-Line Circuit Model
145(3)
6.4 NEXT and FEXT Coupling Factors
148(2)
6.4.1 Using Kb to Predict NEXT
149(1)
6.4.2 Using Kf to Predict FEXT
149(1)
6.5 Crosstalk Worked Example
150(2)
6.5.1 How Well Do Calculations and Simulations Agree?
151(1)
6.6 Practical Considerations
152(3)
6.6.1 Measurements
153(2)
6.7 Correcting Crosstalk
155(3)
6.7.1 Ways to Reduce Coupling
156(1)
6.7.2 Reducing Crosstalk with Termination
157(1)
6.7.3 Circuit Fixes for Crosstalk
157(1)
6.7.4 Debug Strategies
158(1)
References
158(3)
Chapter 7 Introduction to Differential Transmission Lines and Differential Signaling 161(32)
7.1 Introduction
161(1)
7.2 Differential Signals and Noise Rejection
161(2)
7.3 Differential Impedance and Termination
163(8)
7.3.1 How to Terminate Differential Lines with a Common-Mode Component
165(2)
7.3.2 Rebiasing with a pi Terminator
167(1)
7.3.3 Tightly Versus Loosely Coupled Differential Pairs
167(3)
7.3.4 Mode Conversion
170(1)
7.4 Line Codes
171(2)
7.4.1 PAM4
172(1)
7.5 Bit Rate and Data Rate
173(2)
7.5.1 Nyquist Frequency
174(1)
7.6 Block Codes Used in Serial Transmission
175(3)
7.6.1 The 8b/10b Block Code
176(1)
7.6.2 Signal Integrity Debug Use of K Characters
177(1)
7.6.3 Block Code Overhead
178(1)
7.7 Intersymbol Interference and Dispersion
178(1)
7.7.1 Lone 1-Bit Pattern
178(1)
7.8 Eye Diagrams
179(3)
7.8.1 Bit Error Rate
180(2)
7.9 Equalization and De-Emphasis
182(4)
7.9.1 Gigabit Signaling De-Emphasis
182(2)
7.9.2 Passive Equalizers
184(2)
7.10 DC Blocking Capacitors
186(4)
7.10.1 How to Determine the Coupling Capacitor Value
187(3)
References
190(1)
Appendix 7A: Proving Zdiff = 2Z0o with Network Theory
191(2)
Chapter 8 Signal Return Paths and Decoupling 193(28)
8.1 Introduction
193(1)
8.2 Signal Return Paths
193(6)
8.2.1 Return Paths When the Power Plane Is an Unrelated Voltage
195(1)
8.2.2 Crossing Moats
196(3)
8.2.3 Changing Layers
199(1)
8.3 Decoupling Capacitance and Power Supply Impedance
199(6)
8.3.1 Power Supply Noise Voltages and Resonances
200(2)
8.3.2 Resonances
202(1)
8.3.3 Multiple Resonances
203(1)
8.3.4 Techniques for Taming Parallel Resonances
204(1)
8.4 Layout Strategies to Reduce DCAP Interconnect Inductance
205(3)
8.4.1 Use Wide Connecting Trace
205(1)
8.4.2 Do Not Share Vias
205(1)
8.4.3 Using Mutual Inductance Advantageously
206(1)
8.4.4 Using Loss to Improve Resonance
207(1)
8.5 Power/Ground Plane Impedance at High Frequency
208(9)
8.5.1 Power Planes as a Transmission Line
210(1)
8.5.2 Parallel Plane Modes
211(1)
8.5.3 A Standing-Wave Approach
212(2)
8.5.4 Using SPICE Transmission-Line Models to Find Resonances
214(1)
8.5.5 Taming Modal Resonances
215(1)
8.5.6 Embedded Capacitance
216(1)
8.6 Decoupling in the Time Domain
217(2)
References
219(2)
Chapter 9 Ceramic Surface-Mount Capacitors 221(20)
9.1 Introduction
221(1)
9.2 Ceramic Capacitor Temperature Classification
221(5)
9.2.1 How Class-I Capacitors Are Affected by Temperature
223(1)
9.2.2 How Class-II Capacitors Are Affected by Temperature
224(1)
9.3 MLCC Capacitor Body Size Coding
225(1)
9.4 Circuit Model and Frequency Response
226(2)
9.4.1 Capacitor Resonances
226(1)
9.4.2 Practical Capacitor Model
227(1)
9.5 Understanding the Details of ESL, ESR, and Insulation Resistance
228(5)
9.5.1 How ESL Is Affected by Package Size
229(1)
9.5.2 ESR and Dielectric Loss
230(2)
9.5.3 Comparing ESR and ESL
232(1)
9.5.4 Leakage Currents: Insulation Resistance
233(1)
9.6 MLCC Capacitor Aging
233(2)
9.7 Capacitance Change with DC Bias
235(2)
9.8 Piezoelectric Effects
237(1)
9.9 MLCC Usage Guidelines
238(1)
References
239(2)
Chapter 10 Matrices and S-Parameters in Signal Integrity 241(20)
10.1 Introduction
241(1)
10.2 Introducing the Resistance Matrix
241(3)
10.2.1 Mutual Resistance
241(2)
10.2.2 Resistance Matrix at High Frequency
243(1)
10.3 Introducing the Capacitance Matrix
244(3)
10.4 Introducing the Inductance Matrix
247(1)
10.4.1 Internal and External Inductance
247(1)
10.5 Using the Reciprocity Principle to Find Inductance and Capacitance
248(1)
10.6 Introduction to S-Parameters
249(9)
10.6.1 The S-Matrix
250(1)
10.6.2 Reference Impedance
250(1)
10.6.3 S-Parameter File Formats and Viewers
250(1)
10.6.4 S-Parameter Notation
251(2)
10.6.5 Return Loss and the Reflection Coefficient
253(1)
10.6.6 Insertion Loss
254(1)
10.6.7 Measured Results Example
255(1)
10.6.8 Confusion Between RL, IL, and S-Parameters
256(1)
10.6.9 S-Parameter, Return Loss, and Insertion Loss Summary
256(1)
10.6.10 Mixed-Mode S-Parameters
256(2)
References
258(3)
Chapter 11 Layout Techniques and Avoiding High-Speed Signaling Pitfalls 261(28)
11.1 Introduction
261(1)
11.2 Length Matching and Adding Delay
261(4)
11.2.1 Effects of Bends on Delay
262(1)
11.2.2 Effects of Crosstalk and How to Properly Design a Delay Trace
262(2)
11.2.3 Circuit Models
264(1)
11.3 Routing Near the Edge of the Return Plane
265(1)
11.3.1 Change in Impedance
266(1)
11.4 Mitered Corners
266(2)
11.5 Nonfunctional Pads
268(3)
11.6 Fiber-Weave Effect
271(4)
11.6.1 Glass Mat Weaves
271(1)
11.6.2 Problems with Routing
271(2)
11.6.3 Solving FWE by Routing at an Angle
273(1)
11.6.4 Limitations and Problems with Zig-Zag Routing
274(1)
11.6.5 FWE Resonances
274(1)
11.6.6 Choosing a Different Laminate
275(1)
11.7 Routing Through Dense Pin Fields
275(4)
11.7.1 Large Versus Small Anti-Pads
276(1)
11.7.2 Role of Laminate Choice
277(1)
11.7.3 Narrow Escape Traces
277(2)
11.8 Using Companion Vias to Control Impedance
279(1)
11.8.1 Anti-Pad Waveguide Modes and Mode Conversion
279(1)
11.9 Resonances from Stubs
280(2)
11.10 Identifying and Taming Open-Circuited Stubs
282(4)
11.10.1 Stubs from Vias
283(2)
11.10.2 Eliminating Via Stubs with Termination
285(1)
11.10.3 Eliminating Via Stubs by Back Drilling
285(1)
11.10.4 Package Plating Stubs
285(1)
References
286(3)
About the Author 289(2)
Index 291
Stephen C. Thierauf is a signal integrity design engineer at Thierauf Design and Consulting. Previously he was a seniormember of the technical staff at Digital Equipment Corporation and Compaq Computer Corporation, and seniorconsulting hardware engineer at Infiniswitch Corporation. He received his B.S. in Electrical Engineering Technology fromWentworth Institute of Technology.
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