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E-raamat: High Speed Digital Design: Design of High Speed Interconnects and Signaling

(signal integrity lead for PCI Express in Intels Enterprise Platform Technology Division (EPTD), Intel, Columbia, SC, USA), (Jeffrey Ou, Tech Lead in Server Development Group, Intel), (Intel, DuPont, WA, USA)
  • Formaat: PDF+DRM
  • Ilmumisaeg: 17-Aug-2015
  • Kirjastus: Morgan Kaufmann Publishers In
  • Keel: eng
  • ISBN-13: 9780124186675
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High Speed Digital Design: Design of High Speed Interconnects and SignalingSuurem pilt
  • Formaat: PDF+DRM
  • Ilmumisaeg: 17-Aug-2015
  • Kirjastus: Morgan Kaufmann Publishers In
  • Keel: eng
  • ISBN-13: 9780124186675
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High Speed Digital Design discusses the major factors to consider in designing a high speed digital system and how design concepts affect the functionality of the system as a whole. It will help you understand why signals act so differently on a high speed digital system, identify the various problems that may occur in the design, and research solutions to minimize their impact and address their root causes. The authors offer a strong foundation that will help you get high speed digital system designs right the first time.

Taking a systems design approach, High Speed Digital Design offers a progression from fundamental to advanced concepts, starting with transmission line theory, covering core concepts as well as recent developments. It then covers the challenges of signal and power integrity, offers guidelines for channel modeling, and optimizing link circuits. Tying together concepts presented throughout the book, the authors present Intel processors and chipsets as real-world design examples.

  • Provides knowledge and guidance in the design of high speed digital circuits
  • Explores the latest developments in system design
  • Covers everything that encompasses a successful printed circuit board (PCB) product
  • Offers insight from Intel insiders about real-world high speed digital design

Muu info

Holistic guide to signal integrity and interconnects with insider insights of Intel authors
About the Authors/Contributors ix
Chapter 1 Transmission Line Fundamentals
1(26)
Basic Electromagnetics
1(9)
Electromagnetics Field Theory
1(5)
Propagation of Plane Waves
6(4)
Transmission Line Theory
10(8)
Wave Equations on Lossless Transmission Lines
11(3)
Impedance, Reflection Coefficient, and Power Flow on a Lossless Transmission Line
14(2)
Traveling and Standing Waves on a Transmission Line
16(2)
Transmission Line Structures
18(8)
Stripline
19(1)
Microstrip
20(1)
Coplanar Waveguides
21(1)
Novel Transmission Lines
22(4)
References
26(1)
Chapter 2 PCB design for Signal Integrity
27(90)
Differential Signaling
27(4)
Impedance
28(3)
Time Domain Analysis
31(11)
Eye Diagram
31(2)
Jitter
33(9)
Frequency Domain Analysis
42(16)
Spectral Content
42(2)
Insertion Loss
44(2)
Integrated Insertion Loss Noise
46(3)
Return Loss
49(2)
Crosstalk
51(3)
Integrated Crosstalk
54(1)
Signal-to-Noise Ratio
55(3)
Stack-Up Design
58(37)
Impedance Target (Routing Impedance)
59(2)
PCB Losses
61(1)
Dielectric Loss
62(3)
Conductor Loss
65(3)
Crosstalk Mitigation through StackUp
68(5)
Dual Stripline
73(11)
Densely Broadside Coupled Dual Stripline
84(2)
Via Stub Mitigation
86(9)
PCB Layout Optimization
95(20)
Length Matching
96(3)
Fiber Weave Effect
99(2)
Crosstalk Reduction
101(6)
Non-Ideal Return Path
107(3)
Power Integrity
110(1)
Repeaters
111(4)
References
115(2)
Chapter 3 Channel Modeling and Simulation
117(46)
Transmission Lines
117(21)
Causality
117(1)
Checking for Model Causality
118(2)
Causal Frequency-Dependent Model
120(1)
Copper Surface Roughness
121(5)
Conductivity
126(1)
Environmental Impact
127(3)
Model Geometries
130(3)
Corner Models
133(4)
Ideal Assumptions: Homogeneous Impedance
137(1)
Ideal Assumptions: Crosstalk Aggressors
137(1)
Transmitters
138(3)
IBIS Models
138(1)
Spice Voltage Source Model
139(2)
3D Modeling
141(5)
Ports/Terminals
142(2)
Model Analysis Settings
144(2)
Plated-Through-Hole Via
146(4)
Model Techniques
147(1)
Pre-Layout Approximation
148(1)
Pre-Layout Modeling
148(1)
Post-Layout
149(1)
Connectors
150(6)
Connector Variability
150(1)
Signal Selection
150(2)
Separated Via Models
152(1)
Unconnected Pins
153(1)
Physical Features
154(1)
Design Optimization
154(2)
Packages
156(5)
C4 Escape
158(1)
Transmission Line
158(2)
PTH Via
160(1)
BGA Model
160(1)
Signal Selection for 3D Package Structures
161(1)
References
161(2)
Chapter 4 Link Circuits and Architecture
163(36)
Types of Link Circuit Architectures
163(2)
Embedded Clock Architecture
163(1)
Forwarded Clock Architecture
164(1)
Termination
165(5)
DC and AC Coupling
165(1)
Termination Type
166(1)
Termination Circuits
167(1)
Termination Calibration Circuits
168(1)
Termination Detection Circuits
169(1)
Transmitter
170(9)
Transmitter Equalization
171(2)
Transmitter Data Path
173(1)
Current-Mode Driver
174(3)
Voltage-Mode Driver
177(2)
Receiver
179(11)
Receiver Equalization
180(2)
Receiver Data Path
182(2)
Continuous-Time Linear Equalizer
184(1)
Decision Feedback Equalizer
184(2)
Data Sampler
186(1)
Error Sampler
186(1)
Receiver Calibration
187(1)
Receiver Adaptation
188(2)
Clock and Data Recovery
190(5)
Clock and Data Recovery Loop
191(1)
Phase Detectors
192(3)
Forwarded Clock Receiver
195(1)
Delay-Locked Loop
195(1)
Design for Test/Manufacture
195(3)
Analog DFx Features
196(1)
Digital DFx Features
196(2)
References
198(1)
Chapter 5 Measurement and Data Acquisition Techniques
199(22)
Digital Oscilloscope Measurement
199(5)
Real-Time and Equivalent-Time Sampling Scopes
199(1)
Bandwidth
200(2)
Scope Digital Filter Applications
202(2)
TDR Measurements
204(7)
De-skew Differential Pairs with TDR
205(2)
Channel Characterization with TDR
207(2)
Return Loss Measurement with TDR
209(2)
Vector Network Analyzer Measurement
211(8)
What is VNA?
211(2)
VNA Error Sources and Calibration
213(4)
Full Two-Port SOLT Calibration Procedure
217(1)
Example of Measurement Using VNA
217(1)
VNA Measurement Procedure
218(1)
References
219(2)
Chapter 6 Designing and Validating with Intel Processors
221(30)
Designing Systems with Intel Devices
221(16)
Interconnect Model
221(2)
Equalization Models
223(2)
Automatic Equalization Adaptation
225(2)
Performance Analysis
227(5)
Solution from Design of Experiments
232(2)
Solution from Typical Models
234(3)
System Validation with Intel Devices
237(13)
Power-on Preparations
237(1)
Types of I/O Design Validation
238(1)
System Margining Validation Overview
239(5)
DDR System Margining Validation
244(2)
High-Speed Serial I/O Margining Validation
246(3)
Low-Margin Debug Guidance
249(1)
Summary
250(1)
References
250(1)
Index 251
Hanqiao Zhang is an Analog Engineer at Intel and holds a PhD degree in Electromagnetics and Microwave Engineering from Clemson University. Hanqiao joined Intel Xeon product electrical validation team in 2011, where he worked on generations of Intel high-speed digital systems. He developed methodologies for validating high-speed interfaces, such as PCI Express and Quick Path Interface (QPI). Hanqiao is now a signal integrity engineer with Intel Data Center Group. He is involved in mission-critical high-performance servers signal integrity design, bring up, validation and debug. Steve Krooswyk has been at Intel since 2003 when we joined as a signal integrity engineer for EPSD server development. In 2009, Steve transitioned into the signal integrity lead for PCI Express in Intels Enterprise Platform Technology Division (EPTD). In addition to server products, his experience includes involvement in the PCI Express 3.0 and 4.0 specifications. He holds a B.S. and M.S. in electrical engineering from the University of South Carolina. Jeffrey Ou joined Intel in 1999 as an analog design engineer in CMOS RF transceiver design. In 2006, Jeffrey transitioned to Xeon processor product design team in Server Development Group (SDG) developing a serial I/O module configurable for PCI Express and Quick Path Interface (QPI). Since then Jeffrey has been involved in several generations of Xeon products from design to post silicon validation. In 2012, Jeffrey was recognized as a tech lead in SDG, and continued to develop the cutting-edge high speed serial I/O modules for server products. Jeffrey holds a PhD degree in EECS from UC Berkeley and is a member of IEEE.
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