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E-raamat: Integrated Circuit Defect-Sensitivity: Theory and Computational Models

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Spot defects are random phenomena present in every fabrication line. As technological processes mature towards submicron features, the effect of these defects on the functional and parametric behavior of the IC becomes crucial.
Integrated Circuit Defect-Sensitivity: Theory and Computational Models reviews the importance of a defect-sensitivity analysis in comtemporary VLSI design procedures. The modeling of defects in microelectronics technologies is revised from a set theoretical approach as well as from a practical point of view. This way of handling the material introduces the reader step-by-step to critical area analysis through the construction of formal mathematical models. The rigorous formalism developed in this book is necessary to study the construction of deterministic algorithms for layout defect exploration. Without this basis, it would be impossible to scan layouts in the order of 106 objects, or more, in a reasonable time.
The theoretical component of this book is complemented with a set of practical case studies for fault extraction, yield prediction, and IC defect-sensitivity evaluation. These case studies emphasize the fact that by using appropriate formulae combining statistical data with the computed defect-sensitivity, an estimate of the IC's defect tolerance can be obtained at the end of the respective production line. The case studies range from highlighting their geometrical nature as a function of the defect size to more specific situations highlighting layout regions where faults may occur. In addition to the visualization of critical areas, numerical data in the form of tables, graphs and histograms are provided for quantification purposes.
More that, ever smarter, defect-tolerant design strategies have to be devised to attain high yields. Obviously, the work presented in the book is not definitive, and more research will always be useful to advance the field of CAD for manufacturability. This is, of course, one of the interesting challenges imposed by the ever-changing nature of microelectronic technologies. CAD developers and yield practitioners from academia and industry will find that this book lays the foundations for further pioneering work.

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Springer Book Archives
1 Introduction.- 1.1 Approaches to Yield Modeling.- 2 Defect Semantics
and Yield Modeling.- 2.1 Microelectronics Technology.- 2.2 Modeling of
Process Induced Defects and Faults.- 2.3 Statistical Characterization of Spot
Defects.- 2.4 Brief Overview of Historical Yield Models.- 3 Computational
Models for Defect-Sensitivity.- 3.1 Taxonomy of DefectSensitivity Models.-
3.2 Theoretical Foundation of Critical Areas.- 3.3 Susceptible Sites.- 3.4
Critical Regions and Critical Areas.- 3.5 Geometrical Proof of the
Construction of Critical Regions..- 4 Single Defect Multiple Layer (SDML)
Model.- 4.1 Critical Regions for Protrusion Defects.- 4.2 Critical Regions
for Isolated Spot Defects.- 4.3 Critical Regions for Intrusion Defects.- 4.4
A CAD System for SDML Critical Areas.- 4.5 A Spot-Defect Language.- 4.6
Layout Partitioning.- 4.7 Extraction of MultiLayer Susceptible Sites.- 4.8
Defect Mechanisms.- 4.9 Intrusion Defects.- 4.10 IsolatedSpot Defects.- 4.11
Protrusion Defects.- 4.12 Construction of MultiLayer Critical Regions.- 4.13
Computation of MultiLayer Critical Areas.- 4.14 Notes on Implementation.-
4.15 Examples.- 5 Fault Analysis and Multiple Layer Critical Areas.- 5.1
Failure Analysis and Yield Projection of 6TRAM Cells.- 5.2 Fault Weighting.-
5.3 Analysis and Weighting of Defect Induced Faults.- 6 Single Defect Single
Layer (SDSL) Model.- 6.1 Theory of Critical Regions for SDSL Models.- 6.2
SingleLayer Susceptible Sites.- 6.3 Critical Regions for Bridges.- 6.4
Critical Regions for Cuts.- 6.5 Computation of Critical Areas for SDSL
Models.- 6.6 Extraction of SDSL Susceptible Sites.- 6.7 Computation of SDS
Critical Areas.- 6.8 Complexity Analysis.- 6.9 Examples.- 7 IC Yield
Prediction and Single Layer Critical Areas.- 7.1 Sensitivity Analysis.-7.9
Yield Analysis.- 8 Single vs. Multiple Layer Critical Areas.- 8.1 Uncovered
Situations of the SDSL Model.- 8.2 Case Study.- 8.2.1 Comparative Results.-
8.3 Summary and Discussion.- References.- Appendix 1 Sources of Defect
Mechanism.- Appendix 2 End Effects of Critical Regions.- Appendix 3 NMOS
Technology File.