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E-raamat: Integrated Circuit Fabrication

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  • Formaat: 352 pages
  • Ilmumisaeg: 28-Apr-2021
  • Kirjastus: CRC Press
  • Keel: eng
  • ISBN-13: 9781000396447
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Integrated Circuit FabricationSuurem pilt
  • Formaat: 352 pages
  • Ilmumisaeg: 28-Apr-2021
  • Kirjastus: CRC Press
  • Keel: eng
  • ISBN-13: 9781000396447
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This book covers theoretical and practical aspects of all major steps in the fabrication sequence. This book can be used conveniently in a semester length course on integrated circuit fabrication. This text can also serve as a reference for practicing engineer and scientist in the semiconductor industry. IC Fabrication are ever demanding of technology in rapidly growing industry growth opportunities are numerous. A recent survey shows that integrated circuit currently outnumber humans in UK, USA, India and China. The spectacular advances in the development and application of integrated circuit technology have led to the emergence of microelectronic process engineering as an independent discipline. Integrated circuit fabrication text books typically divide the fabrication sequence into a number of unit processes that are repeated to form the integrated circuit. The effect is to give the book an analysis flavor: a number of loosely related topics each with its own background material.
Note: T& F does not sell or distribute the Hardback in India, Pakistan, Nepal, Bhutan, Bangladesh and Sri Lanka.
1 Introduction to Silicon Wafer Processing
1(36)
1.1 Introduction
1(1)
1.2 VLSI Generations
2(3)
1.3 Clean Room
5(3)
1.4 Semiconductor Materials
8(2)
1.5 Crystal Structure
10(3)
1.6 Crystal Defects
13(5)
1.7 Si properties & its Purification
18(2)
1.8 Single Crystal Si Manufacture
20(7)
1.8.1 Czochralski Crystal Growth Technique
20(6)
1.8.2 Float zone Technique (FZ Technique)
26(1)
1.9 Silicon Shaping
27(5)
1.10 Wafer Processing Considerations
32(1)
1.11 Summary
33(4)
Problems
33(2)
References
35(2)
2 Epitaxy
37(38)
2.1 Introduction
37(2)
2.2 Liquid Phase Epitaxy
39(3)
2.3 Vapor Phase Epitaxy/Chemical Vapor Deposition
42(8)
2.3.1 Growth Model and Theoretical Treatment
44(2)
2.3.2 Growth Chemistry
46(2)
2.3.3 Doping
48(1)
2.3.4 Reactors
49(1)
2.4 Defects
50(2)
2.5 Technical Issues for Si Epitaxy by CVD
52(6)
2.5.1 Uniformity/Quality
52(1)
2.5.2 Buried Layer Pattern Transfer
53(5)
2.6 Autodoping
58(1)
2.7 Selective Epitaxy
59(1)
2.8 Low Temperature Epitaxy
60(1)
2.9 Physical Vapor Deposition (PVD)
61(5)
2.9.1 Molecular Beam Epitaxy (MBE)
61(5)
2.10 Silcon-on-Insulator (SOI)
66(1)
2.11 Silicon on Sapphire (SOS)
67(1)
2.12 Silicon on SiO2
68(1)
2.13 Summary
68(7)
Problems
69(1)
References
70(5)
3 Oxidation
75(28)
3.1 Introduction
75(3)
3.2 Growth and Kinetics
78(4)
3.2.1 Dry Oxidation
79(1)
3.2.2 Wet Oxidation
80(2)
3.3 Growth Rate of Silicon Oxide Layer
82(5)
3.4 Impurities effect on the Oxidation Rate
87(2)
3.5 Oxide Properties
89(1)
3.6 Oxide Charges
90(2)
3.7 Oxidation Techniques
92(1)
3.8 Oxide Thickness Measurement
92(3)
3.9 Oxide Furnaces
95(3)
3.10 Summary
98(5)
Problems
98(1)
Reference
99(4)
4 Lithography
103(36)
4.1 Introduction
103(2)
4.2 Optical Lithography
105(1)
4.3 Contact Optical Lithography
106(1)
4.4 Proximity Optical Lithography
106(1)
4.5 Projection Optical Lithography
107(5)
4.6 Masks
112(2)
4.7 Photomask Fabrication
114(1)
4.8 Phase Shifting Mask
115(1)
4.9 Photoresist
116(3)
4.10 Pattern Transfer
119(3)
4.11 Particle-Based Lithography
122(5)
4.11.1 Electron Beam Lithography
122(2)
4.11.2 Electron-Matter Interaction
124(3)
4.12 Ion Beam Lithography
127(2)
4.13 Ultra Violet Lithography
129(1)
4.14 X-Ray Lithography
130(2)
4.15 Comparison of Lithographic Techniques
132(1)
4.16 Summary
133(6)
Problems
134(5)
References
139(1)
5 Etching
139(28)
5.1 Introduction
139(1)
5.2 Etch Parameters
139(2)
5.3 Wet Etching Process
141(2)
5.4 Silicon Etching
143(2)
5.5 Silicon Dioxide Etching
145(1)
5.6 Aluminum Etching
146(1)
5.7 Dry Etching Process
147(1)
5.8 Plasma Etching Process
147(6)
5.8.1 Plasma Chemical Etching Process
150(1)
5.8.2 Sputter Etching Process
151(1)
5.8.3 Reactive Ion Etching (RIE) Process
152(1)
5.9 Inductive coupled Plasma Etching (ICP)
153(1)
5.10 Advantages and Disadvantages of Dry Etching (Plasma Etching) and Wet Etching
154(1)
5.11 Examples of Etching Reactions
154(3)
5.12 Liftoff
157(2)
5.13 Summary
159(8)
Problems
159(1)
References
160(7)
6 Diffusion
167(40)
6.1 Introduction
167(1)
6.2 Atomic Mechanisms of Diffusion
168(3)
6.2.1 Substitutional Diffusion
168(1)
6.2.2 Interstitial Diffusion
169(2)
6.3 Fick's Laws of Diffusion
171(1)
6.4 Diffusion Profiles
172(5)
6.4.1 Constant Source Concentration Distribution
173(2)
6.4.2 Limited Source Diffusion or Gaussian Diffusion
175(2)
6.5 Dual Diffusion Process
177(9)
6.5.1 Intrinsic & Extrinsic Diffusion
179(3)
6.5.2 Diffusivity of Antimony in Silicon
182(1)
6.5.3 Diffusivity of Arsenic in Silicon
182(1)
6.5.4 Diffusivity of Boron in Silicon
183(2)
6.5.5 Diffusivity of Phosphorus in Silicon
185(1)
6.6 Emitter Push Effect
186(2)
6.7 Field-Aided Diffusion
188(1)
6.8 Diffusion Systems
189(4)
6.9 Oxide Masking
193(2)
6.10 Impurity Redistribution During Oxide Growth
195(1)
6.11 Lateral Diffusion
196(1)
6.12 Diffusion in Polysilicon
197(1)
6.13 Measurement Techniques
198(4)
6.13.1 Staining
198(1)
6.13.2 Capacitance-Voltage Plotting (C-V)
199(1)
6.13.3 Four Point Probe (FPP)
200(1)
6.13.4 Secondary Ion Mass Spectroscopy (SIMS)
201(1)
6.13.5 Spreading Resistance Probe (SRP)
201(1)
6.14 Summary
202(5)
Problems
202(1)
References
202(5)
7 Ion Implantation
207(34)
7.1 Introduction
207(2)
7.2 Ionlmplanter
209(4)
7.2.1 Gas System
210(1)
7.2.2 Electrical System
210(1)
7.2.3 Vacuum System
210(1)
7.2.4 Control System
210(1)
7.2.5 Beam Line System
210(3)
7.3 Ion Implant Stop Mechanism
213(4)
7.4 Range and Straggle of Ion Implant
217(3)
7.5 Thickness of Masking
220(2)
7.6 Doping Profile of Ion Implant
222(1)
7.7 Annealing
223(5)
7.7.1 Furnace Annealing
224(2)
7.7.2 Rapid Thermal Annealing (RTA)
226(2)
7.8 Shallow Junction Formation
228(3)
7.8.1 Low Energy Implantation
229(1)
7.8.2 Tilted Ion Beam
229(1)
7.8.3 Implanted Silicides and Polysilicon
230(1)
7.9 High Energy Implantation
231(1)
7.10 Buried Insulator
232(1)
7.11 Summary
233(8)
Problems
234(1)
References
234(7)
8 Film Deposition: Dielectric, Polysilicon and Metallization
241(38)
8.1 Introduction
241(1)
8.2 Physical Vapor Deposition (PVD)
242(3)
8.2.1 Evaporation
243(1)
8.2.2 Sputtering
244(1)
8.3 Chemical Vapor Deposition (CVD)
245(4)
8.4 Silicon Dioxide
249(4)
8.5 Silicon Nitride
253(3)
8.5.1 Locos Methods
254(2)
8.6 Polysilicon
256(1)
8.7 Metallization
257(2)
8.8 Metallization Application in VLSI
259(1)
8.9 Mettalization Choices
260(1)
8.10 Copper Metallization
261(1)
8.11 Aluminium Metallization
262(3)
8.12 Metallization Processes
265(1)
8.13 Deposition Methods
265(1)
8.14 Deposition Apparatus
266(2)
8.15 Liftoff Process
268(1)
8.16 Multilevel Metallization
269(2)
8.17 Characteristics of Metal Thin Film
271(4)
8.18 Summary
275(4)
Problems
275(1)
References
276(3)
9 Packaging
279(16)
9.1 Introduction
279(1)
9.2 Package Types
280(3)
9.3 Packaging Design Considerations
283(1)
9.4 Integrated Circuit Package
284(3)
9.5 VLSI Assembly Technologies
287(4)
9.6 Yield
291(2)
9.7 Summary
293(2)
Problems
293(1)
References
293(2)
10 VLSI Process Integration
295(30)
10.1 Introduction
296(2)
10.2 Fundamental Considerations for IC Processing
298(1)
10.3 NMOS IC Technology
298(3)
10.4 CMOS IC Technology
301(6)
10.4.1 N-Well Process
301(4)
10.4.2 P-Well Process
305(1)
10.4.3 Twin Tub Process
306(1)
10.5 Bipolar IC Technology
307(2)
10.6 Bi-CMOS Technology
309(1)
10.7 Bi-CMOS Fabrication
309(3)
10.8 FinFET
312(3)
10.9 Monolithic and Hybrid Integrated Circuits
315(1)
10.10 IC Fabrication / Manufacturing
316(1)
10.11 Fabrication Facilities
317(5)
10.12 Summary
322(3)
Problems
322(1)
References
322(3)
Appendix 325(8)
Index 333
Kumar Shubham, Delhi Technical Campus, Uttar Pradesh, India

Ankaj Gupta, Delhi Technical Campus, Uttar Pradesh, India
Lisainfo e-raamatute kohta Lisainfo e-raamatute kohta
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