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Robust Low Power Emlbedded SRAM Design: From System to Memory Cell |
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1 | (1) |
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Variability in Advanced Nanometer Technologies: Challeuges and Solutions |
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2 | (1) |
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Subthreshold Circuit Design for Ultar-Low-Power Applications |
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3 | (1) |
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System (!AMS Extensions: New Language New Methods New Applications |
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4 | (1) |
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Session 1: Variability & Statistical Timing |
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Process Variation Aware Performance Analysis of Asynchronous Circuits Considering Spatial Correlation |
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5 | (11) |
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Interpreting SSTA Results with Correlation |
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16 | (10) |
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Residue Arithmetic for Variation-Tolerant Design of Multiply-Add Units |
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26 | (10) |
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Exponent Monte Carlo for Quick Statistical Cirrcuit Simulation |
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36 | (10) |
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Poster Session 1: Circuit Level Techniques |
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Clock Repeater Characterization for Jitter-Aware Clock Tree Synthesis |
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46 | (10) |
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A Hardware Implementation of the User-Centric Display Energy Management |
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56 | (10) |
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On-chip Thermal Modeling Based on SPICE Simulation |
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66 | (10) |
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Switching Noise Optimization in the Wake-Up Phase of Leakage-Aware Power Gating Structures |
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76 | (10) |
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Session 2: Power Management |
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Application-Specific Temperature Reduction Systematic Methodology for 2D and 3D Networks-on-Chip |
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86 | (10) |
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Data-Driven Clock Gating for Digital Filters |
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96 | (10) |
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Power Management and Its Impact on Power Supply Noise |
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106 | (10) |
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Assertive Dynamic Power Management (AsDPM) Strategy for Globally Scheduled RT Multiprocessor Systems |
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116 | (11) |
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Session 3: Low Power Circuits & Technology |
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Design Optimization of Low-Power 90nm CMOS SOC Application Using 0.5V Bulk PMOS Dynamic-Threshold with Dual Threshold (MTCMOS): BP-DTMOS-DT Technique |
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127 | (9) |
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Crosstalk in High-Performance Asynchronous Designs |
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136 | (10) |
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Modeling and Reducing EMI in GALS and Synchronous Systems |
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146 | (10) |
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Low-Power Dual-Edge Triggered State Retention Scan Flip-Flop |
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156 | (9) |
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Hossein Karimiyan Alidash |
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Poster Session 2: System Level Techniques |
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Multi-granularity NoC Simulation Framework for Early Phase Exploration of SDR Hardware Platforms |
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165 | (10) |
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Dynamic Data Type Optimization and Memory Assignment Methodologies |
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175 | (11) |
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Accelerating Embedded Software Power Profiling Using Run-Time Power Emulation |
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186 | (10) |
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Write Invalidation Analysis in Chip Multiprocessors |
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196 | (10) |
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Practical Design Space Exploration of an H264 Decoder for Handheld Devices Using a Virtual Platform |
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206 | (10) |
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BSAA: A Switching Activity Analysis and Visualisation Tool for SoC Power Optimisation |
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216 | (11) |
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Session 4: Power & Timing Optimization Techniques |
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Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-A ware Clustering |
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227 | (10) |
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Low Energy Voltage Dithering in Dual Vpp Circuits |
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237 | (10) |
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Product On-Chip Process Compensation for Low Power and Yield Enhancement |
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247 | (9) |
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Session 5: Self-timed Circuits |
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Low-Power Soft Error Hardened Latch |
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256 | (10) |
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Hossein Karimiyan Alidash |
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Digital Timing Slack Monitors and Their Specific Insertion Flow for Adaptive Compensation of Variabilities |
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266 | (10) |
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Quasi-Delay-Insensitive Computing Device: Methodological Aspects and Practical Implementation |
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276 | (10) |
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The Magic Rule of Tiles: Virtual Delay Insensitivity |
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286 | (11) |
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Session 6: Low Power Circuit Analysis & Optimization |
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Analysis of Power Consumption Using a New Methodology for the Capacitance Modeling of Complex Logic Gates |
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297 | (10) |
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Joao Batista dos Santos Martins |
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Ricardo Augusto da Luz Reis |
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A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR) |
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307 | (10) |
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Routing Resistance Influence in Loading Effect on Leakage Analysis |
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317 | (9) |
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Session 7: Low Power Design Studies |
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Processor Customization for Software Implementation of the AES Algorithm for Wireless Sensor Networks |
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326 | (10) |
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An On-Chip Multi-mode Buck DC-DC Converter for Fine-Grain DVS on a Multi-power Domain SoC Using a 65-nm Standard CMOS Logic Process |
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336 | (11) |
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Energy Dissipation Reduction of a Cardiac Event Detector in the Sub-V, Domain By Architectural Folding |
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347 | (10) |
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A New Optimized High-Speed Low-Power Data-Driven Dynamic (D3L) 32-Bit Kogge-Stone Adder |
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357 | (10) |
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| Author Index |
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367 | |
Lisainfo e-raamatute kohta