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E-raamat: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 22nd International Workshop, PATMOS 2012, Newcastle upon Tyne, UK, September 4-6, 2012, Revised Selected Papers

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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 22nd International Workshop, PATMOS 2012, Newcastle upon Tyne, UK, September 4-6, 2012, Revised Selected PapersSuurem pilt
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This book constitutes the refereed proceedings of the 22nd International Conference on Integrated Circuit and System Design, PATMOS 2012, held in Newcastle, UK Spain, in September 2012. The 25 revised full papers presented were carefully reviewed and selected from numerous submissions. The paper feature emerging challenges in methodologies and tools for the design of upcoming generations of integrated circuits and systems, including reconfigurable hardware such as FPGAs. The technical program focus on timing, performance and power consumption as well as architectural aspects with particular emphasis on modeling, design, characterization, analysis and optimization.
Sleep-Transistor Based Power-Gating Tradeoff Analyses
1(10)
Sven Rosinger
Wolfgang Nebel
Modelling and Analysis of Manufacturing Variability Effects from Process to Architectural Level
11(10)
Chenxi Ni
Ziyad Al Tarawneh
Gordon Russell
Alex Bystrov
Non-invasive Power Simulation at System-Level with SystemC
21(11)
Daniel Lorenz
Philipp A. Hartmann
Kim Gruttner
Wolfgang Nebel
A Standard Cell Optimization Method for Near-Threshold Voltage Operations
32(10)
Masahiro Kondo
Shinichi Nishizawa
Tohru Ishihara
Hidetoshi Onodera
An Extended Metastability Simulation Method for Synchronizer Characterization
42(10)
Salomon Beer
Ran Ginosar
Phase Space Based NBTI Model
52(10)
Reef Eilers
Malte Metzdorf
Sven Rosinger
Domenik Helms
Wolfgang Nebel
Fast Propagation of Hamming and Signal Distances for Register-Transfer Level Datapaths
62(10)
Axel Reimer
Lars Kosmann
Daniel Lorenz
Wolfgang Nebel
Noise Margin Based Library Optimization Considering Variability in Sub-threshold
72(11)
Tobias Gemmeke
Maryam Ashouei
Tobias G. Noll
TCP Window Based DVFS for Low Power Network Controller SoC
83(10)
Eyal-Itzhak Nave
Ran Ginosar
Adaptive Synchronization for DVFS Applications
93(10)
Ghaith Tarawneh
Alex Yakovlev
Muller C-Element Metastability Containment
103(10)
Thomas Polzer
Andreas Steininger
Jakob Lechner
Low Power Implementation of Trivium Stream Cipher
113(8)
J.M. Mora-Gutierrez
C.J. Jimenez-Fernandez
M. Valencia-Barrero
A Generic Architecture for Robust Asynchronous Communication Links
121(10)
Jakob Lechner
Robert Najvirt
Direct Statistical Simulation of Timing Properties in Sequential Circuits
131(11)
Javier Rodriguez
Qin Tang
Amir Zjajo
Michel Berkelaar
Nick van der Meijs
PVTA Tolerant Self-adaptive Clock Generation Architecture
142(13)
Jordi Perez-Puigdemont
Antonio Calomarde
Francesc Moll
On-Chip NBTI and PBTI Tracking through an All-Digital Aging Monitor Architecture
155(11)
Hossein Karimiyan Alidash
Andrea Calimera
Alberto Macii
Enrico Macii
Massimo Poncino
Two-Phase MOBILE Interconnection Schemes for Ultra-Grain Pipeline Applications
166(9)
Juan Nunez
Maria J. Avedillo
Jose M. Quintana
Design of a 150 mV Supply, 2 MIPS, 90nm CMOS, Ultra-Low-Power Microprocessor
175(10)
Pieter Weckx
Nele Reynders
Ilse de Moffarts
Wim Dehaene
Run-Time Measurement of Harvested Energy for Autarkic Sensor Operation
185(9)
Dimitris Bekiaris
Ioannis Kosmadakis
George Stassinopoulos
Dimitrios Soudris
Theodoros Laopoulos
Gregory Doumenis
Stylianos Siskos
Low-Power Delay Sensors on FPGAs
194(11)
Panagiotis Sakellariou
Vassilis Paliouras
Observability Conditions and Automatic Operand-Isolation in High-Throughput Asynchronous Pipelines
205(10)
Arash Saifhashemi
Peter A. Beerel
Dynamic Power Management of a Computer with Self Power-Managed Components
215(10)
Maryam Triki
Yanzhi Wang
Ahmed C. Ammari
Massoud Pedram
Network Time Synchronization: A Full Hardware Approach
225(10)
Jorge Juan
Julian Viejo
Manuel J. Bellido
Case Studies of Logical Computation on Stochastic Bit Streams
235(10)
Peng Li
Weikang Qian
David J. Lilja
Kia Bazargan
Marc D. Riedel
dRail: A Novel Physical Layout Methodology for Power Gated Circuits
245(12)
Jatin N. Mistry
John Biggs
James Myers
Bashir M. Al-Hashimi
David Flynn
Author Index 257
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