Preface |
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ix | |
1 Digital System Modeling and Simulation |
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1 | (8) |
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1 | (1) |
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1.2 Modeling, Synthesis, and Simulation Design |
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1 | (1) |
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1.3 History of Digital Systems |
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2 | (1) |
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1.4 Standard Logic Devices |
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2 | (1) |
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1.5 Custom-Designed Logic Devices |
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3 | (1) |
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1.6 Programmable Logic Devices |
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3 | (1) |
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1.7 Simple Programmable Logic Devices |
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4 | (1) |
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1.8 Complex Programmable Logic Devices |
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5 | (1) |
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1.9 Field-Programmable Gate Arrays |
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6 | (1) |
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1.10 Future of Digital Systems |
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7 | (1) |
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8 | (1) |
2 Number Systems |
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9 | (15) |
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9 | (1) |
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2.2 Bases and Number Systems |
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9 | (2) |
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11 | (2) |
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13 | (1) |
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2.5 Signed and Unsigned Numbers |
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13 | (3) |
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16 | (1) |
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2.7 Addition of Signed Numbers |
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17 | (2) |
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2.8 Binary-Coded Decimal Representation |
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19 | (1) |
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20 | (1) |
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21 | (3) |
3 Boolean Algebra and Logic |
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24 | (22) |
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24 | (1) |
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24 | (1) |
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3.3 Logic Variables and Logic Functions |
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25 | (1) |
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3.4 Boolean Axioms and Theorems |
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25 | (2) |
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3.5 Basic Logic Gates and Truth Tables |
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27 | (1) |
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3.6 Logic Representations and Circuit Design |
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27 | (1) |
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28 | (3) |
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31 | (1) |
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3.9 Logic Design Concepts |
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31 | (1) |
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3.10 Sum-of-Products Design |
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32 | (1) |
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3.11 Product-of-Sums Design |
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33 | (1) |
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34 | (2) |
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3.13 NAND and NOR Equivalent Circuit Design |
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36 | (1) |
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3.14 Standard Logic Integrated Circuits |
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37 | (2) |
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39 | (7) |
4 VHDL Design Concepts |
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46 | (22) |
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46 | (1) |
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4.2 CAD Tool-Based Logic Design |
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46 | (1) |
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4.3 Hardware Description Languages |
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47 | (1) |
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48 | (1) |
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4.5 VHDL Programming Structure |
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48 | (3) |
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4.6 Assignment Statements |
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51 | (1) |
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51 | (4) |
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55 | (1) |
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4.9 VHDL Signal and Generate Statements |
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56 | (2) |
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4.10 Sequential Statements |
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58 | (1) |
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4.11 Loops and Decision-Making Statements |
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59 | (2) |
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61 | (1) |
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4.13 Packages and Components |
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61 | (3) |
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64 | (4) |
5 Integrated Logic |
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68 | (19) |
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68 | (1) |
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68 | (1) |
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69 | (1) |
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5.4 NMOS and PMOS Logic Gates |
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70 | (2) |
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72 | (3) |
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75 | (1) |
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5.7 Practical Aspects of Logic Gates |
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76 | (3) |
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79 | (2) |
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81 | (6) |
6 Logic Function Optimization |
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87 | (18) |
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87 | (1) |
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6.2 Logic Function Optimization Process |
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87 | (1) |
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87 | (2) |
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6.4 Two-Variable Karnaugh Map |
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89 | (1) |
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6.5 Three-Variable Karnaugh Map |
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90 | (1) |
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6.6 Four-Variable Karnaugh Map |
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91 | (2) |
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6.7 Five-Variable Karnaugh Map |
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93 | (1) |
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6.8 XOR and NXOR Karnaugh Maps |
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94 | (1) |
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6.9 Incomplete Logic Functions |
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94 | (2) |
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6.10 Quine-McCluskey Minimization |
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96 | (3) |
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99 | (6) |
7 Combinational Logic |
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105 | (28) |
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105 | (1) |
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7.2 Combinational Logic Circuits |
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105 | (1) |
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106 | (5) |
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7.4 Logic Design with Multiplexers |
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111 | (1) |
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112 | (1) |
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113 | (2) |
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115 | (1) |
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116 | (4) |
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120 | (9) |
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129 | (4) |
8 Sequential Logic |
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133 | (32) |
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133 | (1) |
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8.2 Sequential Logic Circuits |
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133 | (1) |
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134 | (4) |
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138 | (7) |
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145 | (4) |
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149 | (9) |
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158 | (7) |
9 Synchronous Sequential Logic |
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165 | (48) |
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165 | (1) |
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9.2 Synchronous Sequential Circuits |
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165 | (2) |
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9.3 Finite-State Machine Design Concepts |
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167 | (4) |
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9.4 Finite-State Machine Synthesis |
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171 | (7) |
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178 | (2) |
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9.6 One-Hot Encoding Method |
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180 | (2) |
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9.7 Finite-State Machine Analysis |
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182 | (2) |
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9.8 Sequential Serial Adder |
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184 | (4) |
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9.9 Sequential Circuit Counters |
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188 | (7) |
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195 | (4) |
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9.11 Asynchronous Sequential Circuits |
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199 | (2) |
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201 | (12) |
Index |
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