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E-raamat: Introduction to Logic Circuits & Logic Design with VHDL

  • Formaat: PDF+DRM
  • Ilmumisaeg: 15-Sep-2016
  • Kirjastus: Springer International Publishing AG
  • Keel: eng
  • ISBN-13: 9783319341958
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Introduction to Logic Circuits & Logic Design with VHDLSuurem pilt
  • Formaat: PDF+DRM
  • Ilmumisaeg: 15-Sep-2016
  • Kirjastus: Springer International Publishing AG
  • Keel: eng
  • ISBN-13: 9783319341958
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This textbook introduces readers to the fundamental hardware used in modern computers. The only pre-requisite is algebra, so it can be taken by college freshman or sophomore students or even used in Advanced Placement courses in high school. This book presents both the classical approach to digital system design (i.e., pen and paper) in addition to the modern hardware description language (HDL) design approach (computer-based).

This textbook enables readers to design digital systems using the modern HDL approach while ensuring they have a solid foundation of knowledge of the underlying hardware and theory of their designs. This book is designed to match the way the material is actually taught in the classroom. Topics are presented in a manner which builds foundational knowledge before moving onto advanced topics. The author has designed the content with learning goals and assessment at its core. Each section addresses a specific learning outcome that the learner should be able to do after its completion. The concept checks and exercise problems provide a rich set of assessment tools to measure learner performance on each outcome.

This book can be used for either a sequence of two courses consisting of an introduction to logic circuits (Chapters 1-7) followed by logic design (Chapters 8-13) or a single, accelerated course that uses the early chapters as reference material.

Arvustused

Effectively for the undergraduate courses the book can serve the good purpose to understand the digital terminology and logic circuit design. this book is good for beginners and students to understand the digital concepts and basics of VHDL programming. (Amazon.com, November, 2016)

1 Introduction: Analog Vs. Digital
1(6)
1.1 Differences Between Analog and Digital Systems
1(1)
1.2 Advantages of Digital Systems Over Analog Systems
2(5)
2 Number Systems
7(30)
2.1 Positional Number Systems
7(4)
2.1.1 Generic Structure
8(1)
2.1.2 Decimal Number System (Base 10)
9(1)
2.1.3 Binary Number System (Base 2)
9(1)
2.1.4 Octal Number System (Base 8)
10(1)
2.1.5 Hexadecimal Number System (Base 16)
10(1)
2.2 Base Conversion
11(10)
2.2.1 Converting to Decimal
11(3)
2.2.2 Converting from Decimal
14(3)
2.2.3 Converting Between 2n Bases
17(4)
2.3 Binary Arithmetic
21(2)
2.3.1 Addition (Carries)
21(1)
2.3.2 Subtraction (Borrows)
22(1)
2.4 Unsigned and Signed Numbers
23(14)
2.4.1 Unsigned Numbers
23(1)
2.4.2 Signed Numbers
24(13)
3 Digital Circuitry And Interfacing
37(44)
3.1 Basic Gates
37(4)
3.1.1 Describing the Operation of a Logic Circuit
37(2)
3.1.2 The Buffer
39(1)
3.7.3 The Inverter
40(1)
3.1.4 The AND Gate
40(1)
3.1.5 The NAND Gate
41(1)
3.1.6 The OR Gate
41(1)
3.1.7 The NOR Gate
41(1)
3.1.8 The XOR Gate
42(1)
3.1.9 The XNOR Gate
43(1)
3.2 Digital Circuit Operation
44(12)
3.2.1 Logic Levels
44(1)
3.2.2 Output DC Specifications
45(1)
3.2.3 Input DC Specifications
46(1)
3.2.4 Noise Margins
47(1)
3.2.5 Power Supplies
48(3)
3.2.6 Switching Characteristics
51(1)
3.2.7 Data Sheets
51(5)
3.3 Logic Families
56(15)
3.3.1 Complementary Metal Oxide Semiconductors
56(9)
3.3.2 Transistor-Transistor Logic
65(2)
3.3.3 The 7400 Series Logic Families
67(4)
3.4 Driving Loads
71(10)
3.4.1 Driving Other Gates
71(2)
3.4.2 Driving Resistive Loads
73(2)
3.4.3 Driving LEDs
75(6)
4 Combinational Logic Design
81(58)
4.1 Boolean Algebra
81(1)
4.1.1 Operations
82(1)
4.1.2 Axioms
82(1)
4.1.3 Theorems
83(16)
4.1.4 Functionally Complete Operation Sets
98(1)
4.2 Combinational Logic Analysis
99(4)
4.2.1 Finding the Logic Expression from a Logic Diagram
99(1)
4.2.2 Finding the Truth Table from a Logic Diagram
100(1)
4.2.3 Timing Analysis of a Combinational Logic Circuit
101(2)
4.3 Combinational Logic Synthesis
103(9)
4.3.1 Canonical Sum of Products
103(1)
4.3.2 The Minterm List (Σ)
104(2)
4.3.3 Canonical Product of Sums (POS)
106(2)
4.3.4 The Maxterm List (II)
108(2)
4.3.5 Minterm and Maxterm List Equivalence
110(2)
4.4 Logic Minimization
112(17)
4.4.1 Algebraic Minimization
112(1)
4.4.2 Minimization Using Karnaugh Maps
113(12)
4.4.3 Don't Cares
125(1)
4.4.4 Using XOR Gates
126(3)
4.5 Timing Hazards and Glitches
129(10)
5 VHDL (PART 1)
139(36)
5.1 History of Hardware Description Languages
139(4)
5.2 HDL Abstraction
143(3)
5.3 The Modern Digital Design Flow
146(3)
5.4 VHDL Constructs
149(6)
5.4.1 Data Types
150(2)
5.4.2 Libraries and Packages
152(1)
5.4.3 The Entity
152(1)
5.4.4 The Architecture
153(2)
5.5 Modeling Concurrent Functionality in VHDL
155(10)
5.5.1 VHDL Operators
155(3)
5.5.2 Concurrent Signal Assignments
158(1)
5.5.3 Concurrent Signal Assignments with Logical Operators
159(1)
5.5.4 Conditional Signal Assignments
160(1)
5.5.5 Selected Signal Assignments
161(3)
5.5.6 Delayed Signal Assignments
164(1)
5.6 Structural Design Using Components
165(3)
5.6.1 Component Instantiation
166(2)
5.7 Overview of Simulation Test Benches
168(7)
6 MSI Logic
175(20)
6.1 Decoders
175(8)
6.1.1 Example: One-Hot Decoder
175(4)
6.1.2 Example: Seven-Segment Display Decoder
179(4)
6.2 Encoders
183(2)
6.2.1 Example: One-Hot Binary Encoder
183(2)
6.3 Multiplexers
185(2)
6.4 Demultiplexers
187(8)
7 Sequential Logic Design
195(70)
7.1 Sequential Logic Storage Devices
195(15)
7.1.1 The Cross-Coupled In verier Pair
195(1)
7.1.2 Metastability
196(2)
7.1.3 The SR Latch
198(3)
7.1.4 The S'R' Latch
201(3)
7.1.5 SR Latch with Enable
204(1)
7.1.6 The D-Latch
205(2)
7.1.7 The D-Flip-Flop
207(3)
7.2 Sequential Logic Timing Considerations
210(2)
7.3 Common Circuits Based on Sequential Storage Devices
212(7)
7.3.1 Toggle Flop Clock Divider
212(1)
7.3.2 Ripple Counter
213(1)
7.3.3 Switch Debouncing
213(4)
7.3.4 Shift Registers
217(2)
7.4 Finite-State Machines
219(17)
7.4.1 Describing the Functionality of an FSM
219(2)
7.4.2 Logic Synthesis for an FSM
221(7)
7.4.3 FSM Design Process Overview
228(1)
7.4.4 FSM Design Examples
229(7)
7.5 Counters
236(13)
7.5.1 2-Bit Binary Up Counter
236(1)
7.5.2 2-Bit Binary Up/Down Counter
237(3)
7.5.3 2-Bit Gray Code Up Counter
240(2)
7.5.4 2-Bit Gray Code Up/Down Counter
242(2)
7.5.5 3-Bit One-Hot Up Counter
244(1)
7.5.6 3-Bit One-Hot Up/Down Counter
245(4)
7.6 Finite-State Machine's Reset Condition
249(1)
7.7 Sequential Logic Analysis
250(15)
7.7.1 Finding the State Equations and Output Logic Expressions of an FSM
250(1)
7.7.2 Finding the State Transition Table of an FSM
251(1)
7.7.3 Finding the State Diagram of an FSM
252(1)
7.7.4 Determining the Maximum Clock Frequency of an FSM
253(12)
8 VHDL (PART 2)
265(44)
8.1 The Process
265(5)
8.1.1 Sensitivity List
265(1)
8.1.2 The Wait Statement
266(1)
8.1.3 Sequential Signal Assignments
267(2)
8.1.4 Variables
269(1)
8.2 Conditional Programming Constructs
270(6)
8.2.1 If/Then Statements
270(2)
8.2.2 Case Statements
272(1)
8.2.3 Infinite Loops
273(2)
8.2.4 While Loops
275(1)
8.2.5 For Loops
275(1)
8.3 Signal Attributes
276(2)
8.4 Test Benches
278(3)
8.4.1 Report Statement
279(1)
8.4.2 Assert Statement
280(1)
8.5 Packages
281(28)
8.5.7 STD_LOGIC_1164
282(4)
8.5.2 NUMERIC_STD
286(2)
8.5.3 NUMERIC_STD_UNSIGNED
288(1)
8.5.4 NUMERIC_BIT
288(1)
8.5.5 NUMERIC_BIT_UNSIGNED
289(1)
8.5.6 MATH_REAL
289(2)
8.5.7 MATH_COMPLEX
291(1)
8.5.8 TEXTIO and STD_LOGIC_TEXTIO
291(11)
8.5.9 Legacy Packages (STD_LOGIC_ARITH/UNSIGNED/SIGNED)
302(7)
9 Behavioral Modeling Of Sequential Logic
309(32)
9.1 Modeling Sequential Storage Devices in VHDL
309(4)
9.1.1 D-Latch
309(1)
9.1.2 D-Flip-Flop
310(1)
9.1.3 D-Flip-Flop with Asynchronous Reset
310(1)
9.1.4 D-Flip-Flop with Asynchronous Reset and Preset
311(1)
9.1.5 D-Flip-Flop with Synchronous Enable
312(1)
9.2 Modeling Finite-State Machines in VHDL
313(6)
9.2.1 Modeling the States with User-Defined, Enumerated Data Types
315(1)
9.2.2 The State Memory Process
315(1)
9.2.3 The Next State Logic Process
315(1)
9.2.4 The Output Logic Process
316(2)
9.2.5 Explicitly Defining State Codes with Subtypes
318(1)
9.3 FSM Design Examples in VHDL
319(6)
9.3.1 Serial Bit Sequence Detector in VHDL
319(2)
9.3.2 Vending Machine Controller in VHDL
321(2)
9.3.3 2-Bit, Binary Up/Down Counter in VHDL
323(2)
9.4 Modeling Counters in VHDL
325(7)
9.4.1 Counters in VHDL Using the Type UNSIGNED
325(1)
9.4.2 Counters in VHDL Using the Type INTEGER
326(1)
9.4.3 Counters in VHDL Using the Type STD_LOGIC_VECTOR
327(2)
9.4.4 Counters with Enables in VHDL
329(1)
9.4.5 Counters with Loads
330(2)
9.5 RTL Modeling
332(9)
9.5.1 Modeling Registers in VHDL
332(1)
9.5.2 Shift Registers in VHDL
333(1)
9.5.3 Registers as Agents on a Data Bus
334(7)
10 Memory
341(30)
10.1 Memory Architecture and Terminology
341(2)
10.1.1 Memory Map Model
341(1)
10.1.2 Volatile vs. Nonvolatile Memory
342(1)
10.1.3 Read-Only vs. Read/Write Memory
342(1)
10.1.4 Random Access vs. Sequential Access
342(1)
10.2 Nonvolatile Memory Technology
343(9)
10.2.1 ROM Architecture
343(3)
10.2.2 Mask Read-Only Memory
346(1)
10.2.3 Programmable Read-Only Memory
347(1)
10.2.4 Erasable Programmable Read-Only Memory
348(2)
10.2.5 Electrically Erasable Programmable Read-Only Memory
350(1)
10.2.6 FLASH Memory
351(1)
10.3 Volatile Memory Technology
352(10)
10.3.1 Static Random Access Memory
352(3)
10.3.2 Dynamic Random Access Memory
355(7)
10.4 Modeling Memory with VHDL
362(9)
10.4.1 Read-Only Memory in VHDL
362(2)
10.4.2 Read/Write Memory in VHDL
364(7)
11 Programmable Logic
371(14)
11.1 Programmable Arrays
371(4)
11.1.1 Programmable Logic Array
371(1)
11.1.2 Programmable Array Logic
372(1)
11.1.3 Generic Array Logic
373(1)
11.1.4 Hard Array Logic
374(1)
11.1.5 Complex Programmable Logic Devices
374(1)
11.2 Field Programmable Gate Arrays
375(10)
11.2.1 Configurable Logic Block (or Logic Element)
376(1)
11.2.2 Look-Up Tables
377(3)
11.2.3 Programmable Interconnect Points (PIPs)
380(1)
11.2.4 Input/Output Block
381(1)
11.2.5 Configuration Memory
382(3)
12 Arithmetic Circuits
385(32)
12.1 Addition
385(14)
12.1.1 Half Adders
385(1)
12.1.2 Full Adders
386(2)
12.1.3 Ripple Carry Adder (RCA)
388(2)
12.1.4 Carry Look Ahead Adder (CLA)
390(3)
12.1.5 Adders in VHDL
393(6)
12.2 Subtraction
399(3)
12.3 Multiplication
402(6)
12.3.1 Unsigned Multiplication
402(3)
12.3.2 A Simple Circuit to Multiply by Powers of Two
405(1)
12.3.3 Signed Multiplication
405(3)
12.4 Division
408(9)
12.4.1 Unsigned Division
408(3)
12.4.2 A Simple Circuit to Divide by Powers of Two
411(1)
12.4.3 Signed Division
412(5)
13 Computer System Design
417(46)
13.1 Computer Hardware
417(5)
13.1.1 Program Memory
418(1)
13.1.2 Data Memory
418(1)
13.1.3 Input/Output Ports
418(1)
13.1.4 Central Processing Unit
419(1)
13.1.5 A Memory Mapped System
420(2)
13.2 Computer Software
422(9)
13.2.1 Opcodes and Operands
422(1)
13.2.2 Addressing Modes
423(1)
13.2.3 Classes of Instructions
424(7)
13.3 Computer Implementation: An 8-Bit Computer Example
431(26)
13.3.1 Top-Level Block Diagram
431(1)
13.3.2 Instruction Set Design
432(1)
13.3.3 Memory System Implementation
433(5)
13.3.4 CPU Implementation
438(19)
13.4 Architecture Considerations
457(6)
13.4.1 Von Neumann Architecture
457(1)
13.4.2 Harvard Architecture
457(6)
Appendix A List Of Worked Examples 463(6)
Suggested Readings 469(2)
Index 471
Brock J. LaMeres is an Associate Professor in the Department of Electrical and Computer Engineering at Montana State University (MSU). His research interests are in the area of digital systems and engineering education. He has received numerous grants from the National Science Foundation and NASA to study how engineering students learn complex material and how to improve diversity within the field. His research has led to novel instructional methods that have been shown to improve student cognition while simultaneously promoting an inclusive learning environment. He has been honored with numerous teaching awards including the American Society of Engineering Education Section Outstanding Teaching Award, the MSU Presidents Excellence in Teaching Award, the MSU Teaching Innovation Award, the MSU Excellence in Online Teaching Award, and the MSU Provosts Award for Excellence in Teaching and Scholarship.





LaMeres received his Ph.D. in electrical engineering from the University of Colorado, Boulder in December of 2005, his MSEE from the University of Colorado, Colorado Springs in May of 2001, and his BSEE from Montana State University, Bozeman in December of 1998. Prior to joining the MSU faculty, he was an R&D engineer for Hewlett-Packard in Colorado Springs where he designed acquisition systems for electronic test equipment.







LaMeres has published over 80 manuscripts and 2 textbooks in the area of digital systems. LaMeres has also been granted 13 US patents in the area of digital signal propagation. LaMeres is a Senior Member of the Institute of Electrical and Electronic Engineers (IEEE) and a Registered Professional Engineer in the States of Montana and Colorado.
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