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xiii | |
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xv | |
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xvii | |
Preface |
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xix | |
About the Author |
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xxi | |
Acknowledgments |
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xxiii | |
Book Organization |
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xxv | |
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1 | (30) |
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3 | (6) |
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3 | (1) |
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1.2 A Whole New Dimension |
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4 | (1) |
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1.3 Related Terms and Synonyms |
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5 | (2) |
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1.4 Similar yet Unrelated Concepts |
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7 | (2) |
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9 | (16) |
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2.1 General Reversible Computing Problem |
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9 | (1) |
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2.2 Energy-Optimal Computing |
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10 | (1) |
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2.3 Parallel Computing and Synchronization |
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11 | (4) |
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2.3.1 Asynchronous Computing |
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11 | (1) |
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12 | (2) |
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2.3.3 Performance Effects |
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14 | (1) |
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2.4 Processor Architectures |
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15 | (2) |
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2.4.1 Speculative Execution |
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15 | (1) |
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2.4.2 Very Large Instruction Word |
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16 | (1) |
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16 | (1) |
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17 | (1) |
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2.6 Source Code Control Systems |
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18 | (1) |
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19 | (1) |
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20 | (2) |
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2.9 Database Transactions |
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22 | (1) |
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23 | (1) |
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2.11 Additional Applications |
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23 | (2) |
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3 Reversible Computing Spectrum |
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25 | (6) |
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25 | (2) |
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25 | (1) |
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26 | (1) |
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3.2 Partial Reversibility |
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27 | (1) |
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3.3 Unit of Reversibility |
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28 | (3) |
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3.3.1 Reversing a Child's Play |
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28 | (1) |
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3.3.2 Reversing the Movement of Library Books |
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29 | (1) |
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3.3.3 Reversing Different Units of Computation |
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29 | (2) |
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31 | (70) |
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33 | (16) |
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4.1 Logical Computations and Physical Processes |
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33 | (1) |
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4.2 System Theoretic View of Computation |
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34 | (6) |
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4.2.1 A Computation Example |
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35 | (1) |
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4.2.2 Basic Components of Computational Energy |
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35 | (2) |
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4.2.3 Dissipated Energy as Theoretical Energy Cost of Computation |
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37 | (1) |
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4.2.4 Theoretical Lower Bound on Dissipated Energy |
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37 | (1) |
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4.2.5 Reversibility for Zero Dissipated Energy |
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38 | (2) |
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4.3 Reversible Circuits as Bit Compressors |
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40 | (4) |
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4.3.1 Irreversible User Circuit within an Expanded Reversible Circuit |
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40 | (1) |
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4.3.2 Clean and Dirty Bits |
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40 | (1) |
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4.3.3 Custom Computation Circuit |
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41 | (1) |
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4.3.4 General-Purpose Computation Circuit |
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41 | (1) |
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4.3.5 Energy Cost of the Circuit |
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42 | (1) |
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4.3.6 Analogy with Refrigeration |
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42 | (1) |
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4.3.7 Reversibility in the Eye of the Beholder |
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43 | (1) |
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4.4 Deterministic versus Non-Deterministic Reversal |
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44 | (5) |
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4.4.1 Bit Erasure Cost versus Bit Reset Cost |
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45 | (1) |
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4.4.2 Zero Energy Cost Schemes |
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45 | (4) |
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5 Reversibility-Related Paradoxes |
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49 | (22) |
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49 | (1) |
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5.2 Reversibility and Entropy |
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50 | (1) |
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5.3 Ehrenfest's Urn Model |
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51 | (4) |
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5.3.1 Model Configuration and Operation |
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51 | (1) |
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52 | (1) |
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5.3.3 Forward and Reverse Algorithms |
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53 | (1) |
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5.3.4 System versus Computational Reversibility |
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53 | (2) |
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55 | (4) |
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5.4.1 Model Configuration and Operation |
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55 | (1) |
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56 | (1) |
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5.4.3 Forward and Reverse Algorithms |
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57 | (1) |
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5.4.4 An Entropy Function |
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57 | (1) |
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5.4.5 System versus Computational Reversibility |
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57 | (2) |
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5.5 Relation to Maxwell's Demon |
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59 | (4) |
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59 | (1) |
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5.5.2 Setup and Operation |
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60 | (1) |
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5.5.3 Operation as a Computer Program |
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60 | (1) |
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61 | (2) |
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5.6 Relation to Other Paradoxes |
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63 | (3) |
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5.6.1 Loschmidt's Paradox |
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63 | (1) |
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63 | (1) |
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64 | (2) |
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66 | (2) |
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66 | (1) |
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67 | (1) |
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68 | (3) |
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6 Theoretical Computing Models |
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71 | (20) |
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71 | (1) |
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72 | (1) |
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6.3 Sources of Irreversibility in the Turing Machine Model |
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73 | (1) |
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6.4 Definition of a Reversible Model |
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74 | (3) |
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6.4.1 Rewriting Transition Rules: Quintuples to Quadruples |
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75 | (1) |
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6.4.2 Adding History and Output Tapes |
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75 | (1) |
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6.4.3 Canonical Turing Machine Model |
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76 | (1) |
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6.5 Mapping Conventional Model Programs to a Reversible Model |
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77 | (2) |
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6.6 Universality of Computation and Its Reversal |
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79 | (1) |
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6.7 Space and Time Complexity of Reversible Execution |
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80 | (6) |
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6.7.1 Complexity of Simple Reversal with One Segment |
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80 | (1) |
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6.7.2 Partitioning Execution into Two Segments |
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80 | (3) |
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6.7.3 Partitioning Execution into g Segments |
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83 | (1) |
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6.7.4 Optimizing g for Minimal Total Space |
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83 | (1) |
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6.7.5 Generalizing the Time-Space Trade-Off |
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84 | (2) |
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86 | (3) |
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6.8.1 Rules and Objective |
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86 | (1) |
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6.8.2 Analogies with the Reversible Turing Model |
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87 | (1) |
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6.8.3 Complexity Analysis |
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88 | (1) |
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6.8.4 Partial Reversibility |
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88 | (1) |
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89 | (2) |
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7 Relaxing Forward-Only Execution into Reversible Execution |
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91 | (10) |
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7.1 Overview of Paradigms |
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91 | (1) |
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7.2 Compute-Copy-Uncompute Paradigm |
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92 | (1) |
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7.2.1 Equivalence Conditions |
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92 | (1) |
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7.3 Forward-Reverse-Commit Paradigm |
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92 | (3) |
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7.3.1 Equivalence Conditions |
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93 | (1) |
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7.3.2 Sequence Conditions |
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94 | (1) |
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95 | (1) |
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7.4 Undo-Redo-Do Paradigm |
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95 | (2) |
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7.5 Begin-Rollback-Commit Paradigm |
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97 | (4) |
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101 | (148) |
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8 Reversible Programming Languages |
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103 | (24) |
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8.1 Role of Reversible Languages |
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103 | (2) |
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8.2 Language-Level Reversibility Issues |
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105 | (6) |
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8.2.1 Sequence and Recursive Reversal |
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105 | (1) |
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8.2.2 Destructive Updates |
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106 | (1) |
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106 | (1) |
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107 | (2) |
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109 | (1) |
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8.2.6 Additional Control Flow Issues |
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110 | (1) |
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111 | (14) |
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8.3.1 SRL and ESRL Reversible Languages |
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112 | (1) |
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8.3.2 EPA Reversible Language |
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113 | (1) |
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8.3.3 Janus Reversible Language |
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114 | (9) |
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8.3.4 R Reversible Language |
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123 | (2) |
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8.4 Functional and Logic Languages |
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125 | (1) |
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126 | (1) |
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9 Adding Reversibility to Irreversible Programs |
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127 | (20) |
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127 | (2) |
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129 | (7) |
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129 | (1) |
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9.2.2 Periodic Checkpointing |
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130 | (1) |
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9.2.3 Incremental Checkpointing |
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131 | (2) |
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9.2.4 Differential Checkpointing |
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133 | (2) |
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9.2.5 Example Application |
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135 | (1) |
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136 | (8) |
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9.3.1 Automated: Compiler-Based |
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136 | (4) |
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9.3.2 Automated: Interpreter-Based |
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140 | (3) |
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9.3.3 Automated: Library-Based |
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143 | (1) |
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9.3.4 Programmer-Assisted: Source Code-Based |
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143 | (1) |
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9.3.5 Programmer-Assisted: Model-Based |
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144 | (1) |
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144 | (2) |
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146 | (1) |
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147 | (30) |
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10.1 Reversibility of C Language Programs |
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148 | (2) |
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10.2 Source-to-Source Method for Reversible C |
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150 | (3) |
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151 | (1) |
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10.2.2 Definition of Correctness of Reversible Execution |
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151 | (1) |
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10.2.3 Runtime Tape Interface |
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152 | (1) |
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10.2.4 Compilation Phases |
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152 | (1) |
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153 | (7) |
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153 | (1) |
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10.3.2 Side-Effect Expressions |
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153 | (1) |
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154 | (1) |
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10.3.4 Arithmetic Expressions |
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154 | (1) |
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154 | (1) |
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10.3.6 Do While Statements |
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155 | (1) |
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156 | (1) |
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157 | (1) |
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10.3.9 Continue Statements |
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158 | (1) |
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158 | (1) |
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10.3.11 Switch Statements |
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158 | (1) |
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10.3.12 Post-Normalization State |
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159 | (1) |
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160 | (8) |
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10.4.1 Expression Statements |
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160 | (1) |
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161 | (1) |
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161 | (2) |
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10.4.4 Compound Statements |
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163 | (1) |
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10.4.5 Jumps across Nested Blocks |
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163 | (1) |
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164 | (1) |
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165 | (1) |
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166 | (1) |
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167 | (1) |
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168 | (1) |
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168 | (5) |
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10.5.1 Value Recovery or Reconstruction |
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168 | (1) |
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10.5.2 Irreversible and Environment Slices |
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168 | (2) |
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10.5.3 Eliminating Reversal of Initialization |
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170 | (1) |
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10.5.4 Invariant Expressions |
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171 | (1) |
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10.5.5 Common Sub-Expression Elimination |
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172 | (1) |
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10.5.6 Switch Statement Trade-Offs |
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172 | (1) |
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172 | (1) |
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10.6 Tape Size Upper Bounds |
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173 | (2) |
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10.7 Tape Size Determination |
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175 | (2) |
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11 Reversal of Linear Codes |
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177 | (10) |
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11.1 Automated Generation |
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177 | (1) |
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11.2 Example: Fibonacci Sequence |
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178 | (1) |
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11.3 General Linear Codes |
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179 | (1) |
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11.4 Linear Code Reversal Algorithm |
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179 | (5) |
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180 | (1) |
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11.4.2 Matrix Representation |
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180 | (2) |
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11.4.3 Eliminating Singularity |
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182 | (2) |
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184 | (1) |
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11.6 Other Common Linear Codes |
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185 | (2) |
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12 Reversible Random Number Generation |
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187 | (20) |
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12.1 Random Stream Traversal: Forward versus Reverse |
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187 | (2) |
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12.2 Memory-Based Method to Make a Generator Reversible |
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189 | (3) |
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12.3 Pseudorandom Numbers |
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192 | (2) |
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12.3.1 Forward Generation |
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192 | (1) |
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12.3.2 Reversible Generation |
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193 | (1) |
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12.4 Reversible Generation from the Uniform Distribution |
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194 | (3) |
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12.4.1 Open versus Closed Ranges |
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194 | (1) |
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12.4.2 Linear Congruential Generators |
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195 | (1) |
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12.4.3 Counting-Based Generators |
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196 | (1) |
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12.5 Reversible Generation from Invertible Cumulative Distributions |
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197 | (1) |
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12.6 Reversible Generation from Probability Density Functions |
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197 | (7) |
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12.6.1 Reversibility Problem |
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198 | (1) |
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12.6.2 Upper-Bounded Rejection-Based Sampling |
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199 | (3) |
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12.6.3 Upper- and Lower-Bounded Rejection-Based Sampling |
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202 | (2) |
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204 | (3) |
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13 Reversible Memory Allocation and Deallocation |
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207 | (6) |
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13.1 The Problem: Reversible Dynamic Memory |
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207 | (1) |
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13.2 A Simple Solution with Poor Memory Utilization |
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208 | (1) |
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13.3 A Memory-Efficient Solution |
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209 | (4) |
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13.3.1 Verification of Correctness of Allocation |
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210 | (1) |
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13.3.2 Verification of Correctness of Deallocation |
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211 | (2) |
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14 Reversible Numerical Computation |
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213 | (28) |
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14.1 Software and Hardware Views |
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213 | (1) |
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14.2 Sources of Irreversibility in Software |
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214 | (1) |
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14.3 Considerations in Adding Reversibility |
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215 | (1) |
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14.4 Defining Reversibility of Numerical Computation |
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216 | (2) |
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14.4.1 Software-Level Operator Reversal |
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216 | (1) |
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14.4.2 Operators with Constants |
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217 | (1) |
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14.4.3 Operation Sequence Reversal |
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217 | (1) |
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14.4.4 Hardware Circuit-Level Reversal |
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217 | (1) |
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14.5 Reversal of Basic Arithmetic Operations in Software |
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218 | (9) |
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14.5.1 Illustration of Basic Approach |
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218 | (1) |
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219 | (6) |
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14.5.3 Floating Point Operands |
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225 | (2) |
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14.6 Alternative Integer Framework for Reversibility |
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227 | (10) |
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14.6.1 Internal Representation |
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227 | (1) |
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14.6.2 Encoding Certain Error Conditions |
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228 | (1) |
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229 | (1) |
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14.6.4 Signed Values and Modulo Adjustment |
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229 | (1) |
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14.6.5 Backward Compatibility |
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229 | (2) |
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14.6.6 Computing Q and R for Base v |
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231 | (1) |
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14.6.7 Bit Representation Examples |
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231 | (1) |
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14.6.8 Reversible Set of Arithmetic Operations |
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231 | (4) |
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14.6.9 Combined Operation: A Simple Illustration |
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235 | (2) |
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14.6.10 Reversal of Multiple Arithmetic Operations |
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237 | (1) |
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14.7 Reversal of Basic Arithmetic in Hardware |
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237 | (2) |
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239 | (2) |
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15 Reversing a Sorting Procedure |
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241 | (2) |
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16 Implementing Undo--Redo--Do |
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243 | (6) |
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243 | (1) |
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244 | (1) |
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245 | (1) |
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16.4 Deletions and Memory Reclamation |
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246 | (1) |
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16.5 Alternative Implementations |
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247 | (2) |
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16.5.1 Undo and Redo Stacks |
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247 | (1) |
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16.5.2 State Recreation via Reverse Computation |
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247 | (2) |
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249 | (24) |
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17 Reversible Logic Gates |
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251 | (10) |
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251 | (2) |
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17.1.1 Inadequacy of 2-Bit Gates |
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252 | (1) |
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17.1.2 w-Bit Gate Candidates, w ≥ 3 |
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252 | (1) |
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17.2 3-Bit Reversible Gates |
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253 | (1) |
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254 | (2) |
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254 | (1) |
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255 | (1) |
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256 | (3) |
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256 | (1) |
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257 | (1) |
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17.4.3 Increasing the Width to w Bits |
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257 | (2) |
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259 | (1) |
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17.6 Synthesis of Reversible Circuits |
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260 | (1) |
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18 Reversible Instruction Set Architectures |
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261 | (12) |
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18.1 Instruction Set Issues |
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261 | (3) |
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18.1.1 Instruction Set for Memory Operations |
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262 | (1) |
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18.1.2 Instruction Set for Simple Arithmetic |
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262 | (1) |
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18.1.3 Instruction Set for Jumps |
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263 | (1) |
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18.1.4 Implementation Considerations for Jumps |
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264 | (1) |
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18.2 Reversible PDP-10-Like Instruction Set Architecture |
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264 | (2) |
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264 | (1) |
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265 | (1) |
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266 | (1) |
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18.3 Pendulum Instruction Set Architecture |
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266 | (3) |
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268 | (1) |
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268 | (1) |
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268 | (1) |
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268 | (1) |
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269 | (1) |
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18.4 Hardware Interface to Reversible Memory |
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269 | (2) |
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271 | (2) |
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273 | (6) |
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275 | (4) |
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19.1 Phased Transition from Irreversible to Reversible |
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275 | (1) |
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19.2 Need for Additional Progress |
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276 | (2) |
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278 | (1) |
References |
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279 | (14) |
Index |
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293 | |