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E-raamat: Low-Power CMOS Circuits: Technology, Logic Design and CAD Tools

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(CSEM, Neuchatel, Switzerland)
  • Formaat: 436 pages
  • Ilmumisaeg: 03-Oct-2018
  • Kirjastus: CRC Press Inc
  • Keel: eng
  • ISBN-13: 9781351836609
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Low-Power CMOS Circuits: Technology, Logic Design and CAD ToolsSuurem pilt
  • Formaat: 436 pages
  • Ilmumisaeg: 03-Oct-2018
  • Kirjastus: CRC Press Inc
  • Keel: eng
  • ISBN-13: 9781351836609
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The power consumption of integrated circuits is one of the most important problems for high-performance chips and portable devices. This resource for practitioners addresses the design of low-power integrated circuits in deep sub-micron technologies. Twenty-two contributions by Piguet (CSEM Switzerland) and other specialists discuss such topics as on-chip optical interconnects, low-power arithmetic operators, and adiabatic and clock-powered circuits. The final section focuses on the use of CAD tools for designing low-power circuits. The material in this volume is taken from Low-Power Electronics Design (CRC, 2004). Annotation ©2006 Book News, Inc., Portland, OR (booknews.com)

The power consumption of microprocessors is one of the most important challenges of high-performance chips and portable devices. In chapters drawn from Piguet's recently published Low-Power Electronics Design, Low-Power CMOS Circuits: Technology, Logic Design, and CAD Tools addresses the design of low-power circuitry in deep submicron technologies. It provides a focused reference for specialists involved in designing low-power circuitry, from transistors to logic gates.

The book is organized into three broad sections for convenient access. The first examines the history of low-power electronics along with a look at emerging and possible future technologies. It also considers other technologies, such as nanotechnologies and optical chips, that may be useful in designing integrated circuits. The second part explains the techniques used to reduce power consumption at low levels. These include clock gating, leakage reduction, interconnecting and communication on chips, and adiabatic circuits. The final section discusses various CAD tools for designing low-power circuits. This section includes three chapters that demonstrate the tools and low-power design issues at three major companies that produce logic synthesizers.

Providing detailed examinations contributed by leading experts, Low-Power CMOS Circuits: Technology, Logic Design, and CAD Tools supplies authoritative information on how to design and model for high performance with low power consumption in modern integrated circuits. It is a must-read for anyone designing modern computers or embedded systems.
PART I Technologies and Devices
History of Low-Power Electronics
1(1)
Christian Piguet
Introduction
1(1)
Early Computers
2(1)
Power Consumption of Early Computers
Reused Concepts for Low Power
Transistors and Integrated Circuits
3(5)
Invention of the Transistor
Invention of the IC
MOS Transistors
Early Microprocessors
RISC Machines
Low-Power Consumer Electronics
8(2)
First Electronic Wristwatch
Electronic Watches in Japan
Electronic Watches in the U.S.
The Dramatic Increase in Power
10(3)
Low-Power Workshops
Low-Power Design Techniques
Conclusion
13
References
14
Evolution of Deep Submicron Bulk and SOI Technologies
1(1)
Marc Belleville
Olivier Faynot
Introduction
1(1)
Overview of ITRS Roadmap
2(1)
Major Evolutions
Bulk CMOS Technologies
SOI Technologies
Transistors Saturation and Subthreshold Currents
3(3)
Subthreshold Leakage and Voltage Limits
SOI Benefits
Bulk CMOS Design Solutions for Subthreshold Leakage
SOI CMOS Design Solutions for Subthreshold Leakage
Gate and Other Tunnel Currents
6(3)
Tunneling Effects
Gate Current
Design Issues and Possible Solutions
High-K Materials and Other Device Options
Statistical Dispersion of Transistor Electrical Parameters
9(1)
Dopant Fluctuation
Design Issues and Possible Solutions
Physical and Electrical Gate Oxide Thickness
10(2)
Poly Depletion
Quantum Effects
Circuit Dynamic Performances
Innovative Transistor Architectures
12(2)
Strained Silicon
Multiple Gate Devices
Conclusion
14
References
14
Leakage in CMOS Nanometric Technologies
1(1)
Antoni Ferre
Joan Figueras
Introduction
1(1)
ILEAK Components of MOSFET Devices
1(10)
Gate Tunneling Currents
Subthreshold Leakage Currents
Gate-Induced Drain Leakage Currents
Junction Leakage Currents
Punchthrough Currents
Scaling
11(2)
Scaling of VTH and its Impact on Subthreshold Current
Short-Channel Effects
Gate-Tunneling Currents
Circuit Level
13(3)
Conclusions
16
References
17
Microelectronics, Nanoelectronics, and the Future of Electronics
1(1)
Jing Wang
Mark Lundstrom
Introduction
1(1)
The Silicon MOSFET as a Nanoelectronic Device
2(2)
What Is Nanotechnology?
Silicon MOSFETs in the Nanometer Regime
Ultimate Limits of the Silicon MOSFET
4(1)
Practical Limits of the Silicon MOSFET
5(1)
Beyond the Silicon MOSFET
5(3)
Carbon Nanotube Transistors
Organic Molecular Transistors
MOSFETs with New Channel Materials and Semiconductor Nanowire Transistors
Beyond the FET
8(1)
Single-Electron Transistors
Spin Transistors
From Microelectronics to Nanoelectronics
9(1)
Conclusion
10(1)
Acknowledgments
10
References
10
Advanced Research in On-Chip Optical Interconnects
1(1)
Ian O'Connor
Frederic Gaffiot
The Interconnect Problem
1(3)
Analysis of Electrical Interconnect Performance
The Optical Alternative
Identified Applications
Top-Down Link Design
4(2)
Technology
Design Requirements
Passive Photonic Devices for Signal Routing
6(3)
Waveguides
Resonators
Photonic Crystals
Active Devices for Signal Conversion
9(1)
III-V Sources
Detectors
Conversion Circuits
10(2)
Driver Circuits
Receiver Circuits
Bonding Issues
12(2)
Link Performance (Comparison of Optical and Electrical Systems)
14(2)
Research Directions
16(2)
Network Links
Acknowledgments
18
References
18
PART II Low-Power Circuits
Modeling for Designing in Deep Submicron Technologies
1(1)
Daniel Auvergne
Philippe Maurine
Nadine Azemard
Introduction
1(1)
Current Modeling
2(2)
Maximum Switching Current
Fast Input Range
Slow Input Range
Extension to Gates
Definition of Metric for Performance
4(6)
Metric for the Transition Time
Metric for the Process
Supply Voltage and Temperature Sensitivity
Metric for the Delay
Metric for the Short-Circuit Power Dissipation
Application to a Standard Cell Library
10(3)
Continuous Representation of Standard Cell Performance
Calibration Procedure
Validation
Application to Low-Power Design
13(3)
Rule for Slope Control
Application
Validation
Conclusion
16
References
16
Logic Circuits and Standard Cells
1(1)
Christian Piguet
Introduction
1(1)
Logic Families
1(6)
Static CMOS Logic
Branch-Based Logic
Transmission Gates
N-Pass Logic
Dynamic Precharged Logic
Memory Elements
Double-Edge Triggered Flip-Flops
Low-Power and Standard Cell Libraries
7(6)
Gated Clocks
Latch-Based Designs
Cell Drives
Complex Gate Decomposition
Standard Cell Libraries
Static Power
Logic Styles for Specific Applications
13(3)
Library Cells for Self-Timed Design
Library Cells for Cryptographic Applications
SEU-Tolerant Logic
Conclusion
16
References
17
Low-Power Very Fast Dynamic Logic Circuits
1(1)
Jiren Yuan
Introduction
1(1)
Single-Clock Latches and Flip-Flops
2(6)
TSPC Latches and Flip-Flops
Differential Single-Clock Latches and Flip-Flops
Power-Delay Comparison
High-Throughput CMOS Circuit Techniques
8(4)
TSPC Pipeline
TSPC Double Pipeline
Clock-and-Data Precharged Circuit Technique
United Connection Rules of TSPC and CDPD Stages
Fast and Efficient CMOS Functional Circuits
12(6)
Dividers and Ripple Counters
Synchronous Counter
Nonbinary Divider and Prescaler
Adder and Accumulator
Bit-Serial Comparator and Sorter
The Future of Dynamic Logic
18(1)
Conclusion
18
References
19
Low-Power Arithmetic Operators
1(1)
Arnaud Tisserand
Introduction
1(1)
Addition
2(5)
1-Bit Addition Cells
Sequential Adder
Propagate and Generate Mechanisms
Carry Select Adder
Carry Skip Adder
Logarithmic Adders
Power/Delay Comparison
Redundant Adders
Multiplication
7(5)
Partial Products Generation
Reduction Trees
Final Addition
Fused Multiply and Add
Truncated Multiplication
Square
Other Operations, Number Systems, and Constraints
12
Division and Square Root
Elementary Functions Evaluation
Floating-Point Arithmetic
Logarithmic Number System
Technology Evolution
References
14
Circuits Techniques for Dynamic Power Reduction
1(1)
Dimitrios Soudris
Introduction
1(1)
Dynamic Power Consumption Component
1(2)
Power Reduction Approaches
Circuit Parallelization
3(6)
Memory Parallelization
Parallelized Shift Register
Serial-Parallel Converter
Linear Feed-Back Shift Registers
Double-Edge Triggered Flip-Flop
Voltage Scaling-Based Circuit Techniques
9(6)
Multiple Voltages Techniques
Low Voltage Swing
Circuit Technology-Independent Power Reduction
15(2)
Precomputation
Retiming
Synthesis of FSMs with Gated Clocks
Circuit Technology-Dependent Power Reduction
17(2)
Path Balancing
Technology Decomposition
Technology Mapping
Conclusions
19
References
19
VHDL for Low Power
1(1)
Amara Amara
Philippe Royannez
Introduction
1(1)
Basics
2(2)
Power Consumption
RTL Coding Applicability to Power Reduction
Latch Inference
Direct Component Instantiation
Explicit-State Encoding
Glitch Reduction
4(1)
Gate-Level Control
Block-Level Control
Clock Gating
5(8)
Flip-Flop-Based Design
Issues in Clock Gating of DFF-Based Design
Latch-Based Design
Issues in Latch-Based Design
Finite-State Machines
13(2)
Gated-Clock FSM
State Encoding
FSM Partitioning
Datapaths
15(4)
Precomputation Design Techniques
Guarded Evaluation Design Techniques
Control-Signal Gating Design Techniques
Bus Encoding
19(1)
Bus Invert Encoding
Other Bus Encoding Techniques
Conclusion
20(1)
Acknowledgments
21
References
21
Clocking Multi-GHz Systems
1(1)
Vojin G. Oklobdzija
Introduction
1(1)
Clock Distribution
Clocking Considerations in Sequential Systems
2(6)
Time Borrowing and Absorption of Clock Uncertainties
Asynchronous Systems
8(1)
Globally Asynchronous Locally Synchronous Systems
8(2)
Conclusion
10
To Probe Further
10(1)
References
10
Circuit Techniques for Leakage Reduction
1(1)
Kaushik Roy
Amit Agarwal
Chris H. Kim
Introduction
1(1)
Leakage Components
2(2)
Subthreshold Leakage
Gate Leakage
Source/Substrate and Drain/Substrate P-N Junction Leakage
Circuit Techniques to Reduce Leakage in Logic
4(1)
Design Time Techniques
4(2)
Dual Threshold CMOS
Multiple Supply Voltage
Runtime Standby Leakage Reduction Techniques
6(4)
Leakage Control Using Transistor Stacks (Self-Reverse Bias)
Sleep Transistor
Variable Threshold CMOS (VTCMOS)
Runtime Active Leakage Reduction Techniques
10(2)
Dynamic Vdd Scaling (DVS)
Dynamic Vth Scaling (DVTS)
Circuit Techniques to Reduce Leakage in Cache Memories
12
References
15
Low-Power and Low-Voltage Communication for SoCs
1(1)
Christer Svensson
Introduction
1(1)
Basics of Wires
2(3)
General
Interconnect Delays
Wires with Repeaters
Power Consumption Related to Interconnect
5(3)
Basics
Power Consumption Related to Drivers and Repeaters
Power Related to Precharged Buses
Strategies for Power Savings in Interconnect
8(5)
Introduction
Reduced Voltage Swing
Reduced Interconnect Activity
Power Savings in Drivers and Repeaters
Off-Chip Interconnect
Charge Recovery Techniques
A Comment about Optical Interconnect
13(1)
Conclusion
13
References
14
Adiabatic and Clock-Powered Circuits
1(1)
Lars Svensson
Introduction
1(1)
The Adiabatic-Charging Principle
1(2)
Implementation Issues
3(10)
Adiabatic Logic
Adiabatic Buffering
Adiabatic Power Supplies
Conclusion
13
References
14
Weak Inversion for Ultimate Low-Power Logic
1(1)
Eric A. Vittoz
Introduction
1(1)
MOS Model in Weak Inversion and Basic Assumptions
2(1)
Static CMOS Inverter
3(2)
Dynamic Behavior of the CMOS Inverter
5(1)
State Transition
Currents and Charges
Behavior of the Inverter for Standard Transitions
6(5)
Definition and Delay Time
Currents and Charges
Ring Oscillator
Power-Delay Product
Minimum Delay Time in Weak Inversion
Effect of Entering Moderate and Strong Inversion
11(2)
Transistor Model
Required Voltage Swing
Degeneration of Logic States
Extension to Logic Gates and Numerical Examples
13(1)
Practical Considerations and Limitations
14(3)
Low-Voltage Power Source
Low-Threshold and Threshold Adjustment
Symmetry and Matching
Process Scaling and Short-Channel Effects
System Architecture and Applications
Conclusion
17
References
17
Robustness of Digital Circuits at Lower Voltages
1(1)
Harry Veendrick
Introduction
1(2)
Signal Integrity
3(10)
Cross Talk and Signal Propagation
Supply and Ground Bounce
Substrate Bounce
EMC
Soft Errors
Transistor Matching
Statistical Timing Analysis
Signal Integrity Summary and Trends
Reliability
13(8)
Electromigration
Hot-Carrier Degradation
Negative Bias Temperature Instability (NBTI)
Latch-Up
Electro-Static Discharge (ESD)
Charge Injection during the Fabrication Process
Reliability Summary and Trends
Conclusion
21(2)
Acknowledgment
23
References
24
PART III CAD Tools for Low-Power
High-Level Power Estimation and Analysis
1(1)
Wolfgang Nebel
Domenik Helms
Introduction
1(2)
Analysis vs. Estimation
Sources of Power Consumption
Generic Design Flow for Low-Power Applications
3(3)
Generic Power Estimation and Analysis Flow
Low-Power Design Flow
System-Level Power Analysis
6(5)
Objectives of System-Level Design
Analysis of an Implementation Model
Analysis of an Execution Model
Algorithmic-Level Power Estimation and Analysis
11(9)
Software Power Analysis
Algorithmic-Level Power Estimation for Hardware Implementations
ORINOCO: A Tool for Algorithmic-Level Power Estimation
20(2)
Conclusion
22
References
22
Power Macro-Models for High-Level Power Estimation
1(1)
Enrico Macii
Massimo Poncino
Introduction
1(1)
RTL Power Modeling
2(6)
Model Granularity
Model Parameters
Model Semantics
Model Construction and Storage
Accuracy Issues
RTL Power Macro-Modeling and Estimation
8(5)
Macro-Modeling Flow
Macro-Modeling Example
RTL Power Estimation Based on Macro-Modeling
RTL Power Estimation in Real-Life Settings
13(2)
Power Models of Non-Synthetic Operators
Conclusions
15(1)
Acknowledgments
16
References
16
Synopsys Low-Power Design Flow
1(1)
Renu Mehra
Barry Pangrle
Introduction
1(1)
Clock Gating
2(1)
Module-Level Clock Gating
Register-Level Clock Gating
Cell-Level Clock Gating
Automated Clock Gating at the Register Level
3(4)
Practical Gating Circuits
Clock Latency
Effect of Clock Skew
Clock-Tree Synthesis
Physical Clock Gating
Testability Concerns
Operand Isolation
7(1)
Logic Optimization
8(3)
Sizing and Buffering
Technology Mapping
Phase Assignment
Algebraic Transformations
Leakage Control---Managing Thresholds
11(2)
Multi-Threshold Design
Variable Threshold Biasing
Voltage Scaling
13(2)
Modeling Basics
15(3)
Switching Power
Internal Power
Leakage or Static Power Modeling
Scalable Polynomial Power Models (SPPMs)
Modeling Activity
Analysis Flows
18(1)
Conclusion
19
References
19
Magma Low-Power Flow
1(1)
Ed Huijbregts
Lars Kruse
Eric Seelen
Introduction
1(1)
Integrated Tool Suite
Power Dissipation
2(2)
Dynamic Power
Static Power
Power Analysis
4(1)
Activity
Interconnect Modeling
Multiple Corner Analysis
Power Optimization
5(4)
Power Management
Gate Sizing
Multiple Thresholds
Rail Analysis
9(4)
Analysis Flow
Voltage-Drop-Induced Analysis
Abstraction
What-If Analysis
Partial Grids
Electromigration
Power Grid Synthesis
13(1)
Grid Synthesis
Packaging Considerations
Conclusion
14
Sequence Design Flow for Power-Sensitive Design
1(1)
Jerry Frenkil
Introduction
1(1)
Design Flow Overview
2(3)
CMOS Power Consumption
Power-Sensitive Design Challenges
Feed Forward Design Flow
Sequence Tools for Power-Sensitive Design
5(11)
PowerTheater
Using PowerTheater
PhysicalStudio
Using PhysicalStudio
CoolTime
Using CoolTime
A Design Example
16(1)
High-Level Design
Physical Design
Electrical Sign-Off
Conclusion
17
References
17
Index 1
Christian Piguet
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