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E-raamat: Low-Power Design of Nanometer FPGAs: Architecture and EDA

(Staff Engineer in the timing and power group at Actel Corporation.), (Tenured Associate Professor at the Department of Electrical and Computer Engineering, University of Waterloo.)
  • Formaat: PDF+DRM
  • Sari: Systems on Silicon
  • Ilmumisaeg: 14-Sep-2009
  • Kirjastus: Morgan Kaufmann Publishers In
  • Keel: eng
  • ISBN-13: 9780080922348
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Low-Power Design of Nanometer FPGAs: Architecture and EDASuurem pilt
  • Formaat: PDF+DRM
  • Sari: Systems on Silicon
  • Ilmumisaeg: 14-Sep-2009
  • Kirjastus: Morgan Kaufmann Publishers In
  • Keel: eng
  • ISBN-13: 9780080922348
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Low-Power Design of Nanometer FPGAs Architecture and EDA is an invaluable reference for researchers and practicing engineers concerned with power-efficient, FPGA design. State-of-the-art power reduction techniques for FPGAs will be described and compared. These techniques can be applied at the circuit, architecture, and electronic design automation levels to describe both the dynamic and leakage power sources and enable strategies for codesign.
  • Low-power techniques presented at key FPGA design levels for circuits, architectures, and electronic design automation, form critical, "bridge" guidelines for codesign
  • Comprehensive review of leakage-tolerant techniques empowers designers to minimize power dissipation
  • Provides valuable tools for estimating power efficiency/savings of current, low-power FPGA design techniques

Muu info

The essential guide to state-of-the-art, Low-Power Design for nanometer FPGAs!
Author Bios xiii
FPGA Overview: Architecture and CAD
1(30)
Introduction
2(3)
FPGA Logic Resources Architecture
5(5)
Altera Stratix IV Logic Resources
6(1)
Xilinx Virtex-5 Logic Resources
7(1)
Actel ProASIC3/IGLOO Logic Resources
8(1)
Actel Axcelerator Logic Resources
9(1)
FPGA Routing Resources Architecture
10(2)
CAD for FPGAs
12(5)
Logic Synthesis
12(1)
Packing
13(1)
Placement
14(2)
Timing Analysis
16(1)
Routing
16(1)
Versatile Place and Route (VPR) CAD Tool
17(14)
VPR Architectural Assumptions
17(5)
Basic Logic Packing Algorithm: VPack
22(2)
Timing-Driven Logic Block Packing: T-VPack
24(2)
Placement: VPR
26(2)
Routing: VPR
28(3)
Power Dissipation in Modern FPGAs
31(10)
CMOS Technology Scaling Trends and Power Dissipation in VLSI Circuits
32(3)
Dynamic Power in FPGAs
35(1)
Leakage Power in FPGAs
35(6)
CMOS Device Leakage Mechanisms
35(3)
Current Situation of Leakage Power in Nanometer FPGAs
38(3)
Power Estimation in FPGAs
41(44)
Introduction
42(2)
Power Estimation in VLSI: An Overview
44(6)
Simulation-Based Power Estimation Techniques
44(3)
Probabilistic-Based Power Estimation Techniques
47(3)
Commercial FPGA Power Estimation Techniques
50(3)
Spreadsheet Power Estimation Tools
50(1)
CAD Power Estimation Tools
51(2)
A Survey of FPGA Power Estimation Techniques
53(5)
Linear Regression-Based Power Modeling
54(2)
Probabilistic FPGA Power Models
56(1)
Look-up Table-Based FPGA Power Models
56(2)
A Complete Analytical FPGA Power Model under Spatial Correlation
58(27)
Spatial Correlation and Signal Probability Calculations
58(2)
Exploration Phase: Locating Spatial Correlation
60(1)
Signal Probabilities Calculation Algorithm under Spatial Correlation
61(4)
Power Calculations Due to Glitches
65(1)
Signal Probabilities and Power Dissipation
66(5)
Results and Discussion
71(14)
Dynamic Power Reduction Techniques in FPGAs
85(54)
Multiple Supply Voltage
86(13)
Predefined Dual-VDD Dual-Vth FPGAs
87(5)
Programmable Dual-VDD
92(5)
Other Dual-VDD FPGA Techniques
97(2)
Reducing Glitches in FPGAs
99(23)
Glitch Power Reduction Using Delay Insertion
99(6)
Multiphase Flip-Flop Insertion for Glitch Power Reduction in FPGAs
105(10)
Negative Edge Flip-Flop Insertion for Glitch Power Reduction in FPGAs
115(2)
Behavioral Synthesis with Flip-Flop Insertion for Glitch Power Reduction in FPGAs
117(5)
CAD Techniques for Reducing Dynamic Power in FPGAs
122(17)
Power Reduction Techniques during Technology Mapping
122(10)
Power Reduction Techniques during Clustering
132(2)
Power Reduction Techniques during Placement and Routing
134(5)
Leakage Power Reduction in FPGAs Using MTCMOS Techniques
139(56)
Introduction
140(3)
MTCMOS FPGA Architecture
143(5)
Sleep Transistor Design and Discharge Current Processing
148(10)
Sleep Transistor Sizing
148(3)
Mutually Exclusive Discharge Current Processing
151(2)
Logic-Based Discharge Current Processing
153(1)
Topological Sorting and Discharge Current Addition
154(4)
Activity Profile Generation
158(16)
Connection-Based Activity Profile Generation Algorithm (CAP)
160(6)
LAP Generation
166(8)
Activity Packing Algorithms
174(6)
AT-VPack
175(2)
Force-Based Activity T-VPack (FAT-VPack)
177(1)
Timing-Driven MTCMOS (T-MTCMOS) AT-VPack
178(2)
Power Estimation
180(1)
Results and Discussion
181(14)
Experimental Setup
182(1)
Algorithm Comparison
183(3)
Impact of Activity Packing on Performance
186(3)
Leakage Savings Breakdown
189(2)
Impact of Utilization and ON Time on Leakage Savings
191(2)
Impact of the Sleep Region Size
193(1)
Scalability of the Proposed Algorithms with Technology Scaling
194(1)
Leakage Power Reduction in FPGAs Through Input Pin Reordering
195(26)
Leakage Power and Input State Dependency in FPGAs
197(7)
Subthreshold Leakage Current
197(3)
Gate Leakage
200(1)
Low-Leakage States in Pass-Transistor Multiplexers
201(2)
Leakage Power in Inverters/Buffers
203(1)
Proposed Input Pin Reordering Algorithm
204(8)
LPR Algorithm
205(5)
Routing Switch Pin Reordering (RPR) Algorithm
210(2)
Experimental Results
212(7)
Pin Reordering and Performance
215(3)
Pin Reordering and Technology Scaling
218(1)
Conclusion
219(2)
References 221(16)
Index 237
Hassan Hassan is currently a staff engineer in the timing and power group at Actel Corporation. He has authored/coauthored more than 20 papers in international journals and conferences. His research interests include integrated circuit design and design automation for deep submicron VLSI systems. He is also a member of the program committee for several IEEE conferences. Dr. Hassan received his Ph.D. in electrical engineering from the University of Waterloo, Waterloo, ON, Canada, in 2008. Mohab Anis is a tenured Associate Professor at the Department of Electrical and Computer Engineering, University of Waterloo. During 2009, he was with the Electronics Engineering Department at the American University in Cairo. Dr. Anis received his Ph.D. in electrical engineering from the University of Waterloo, Waterloo, ON, Canada, in 2003. Dr. Anis is an Associate Editor of the IEEE Transactions on Circuits and Systems - II, Microelectronics Journal, Journal of Circuits, Systems and Computers, ASP Journal of Low Power Electronics, and VLSI Design. He was awarded the 2009 Early Research Award, the 2004 Douglas R. Colton Medal for Research Excellence in recognition of excellence in research leading to new understanding and novel developments in Microsystems in Canada and the 2002 International Low-Power Design Contest.
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