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E-raamat: Model Generation in Electronic Design

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Model Generation in Electronic Design covers a wide range of model applications and research. The book begins by describing a model generator to create component models. It goes on to discuss ASIC design and ASIC library generation. This section includes chapters on the requirements for developing and ASIC library, a case study in which VITAL is used to create such a library, and the analysis and description of the accuracy required in modeling interconnections in ASIC design.
Other chapters describe the development of thermal models for electronic devices, the development of a set of model packages for VHDL floating point operations, a techniques for model validation and verification, and a tool for model encryption.
Model Generation in Electronic Design is an essential update for users, vendors, model producers, technical managers, designers and researchers working in electronic design.

Muu info

Springer Book Archives
1. A Flexible Generator of Component Models.- 1.1. Introduction.- 1.2.
G&D Generator.- 1.3. A Flexible Generator.- 1.4. Implementation of the
Generator.- 1.5. Experimental Results.- 1.6. Conclusions and Future Work.-
2.
What Makes an Asic Library Sign-Off.- 2.1. Introduction.- 2.2. Testing.- 2.3.
Accuracy.- 2.4. Library Creation.- 2.5. Conclusion.-
3. A Case History in
Building Vital-Compliant Models.- 3.1. Introduction: from VHDL to VITAL.-
3.2. Evolution of VITAL Specification.- 3.3. Simulation Performances.- 3.4.
Conclusion and Future Work.-
4. Modeling Multiple Driver Net Delay in
Simulation.- 4.1. Wire Delay.- 4.2. Wire Delay Modeling Alternatives.- 4.3.
Modeling Wire Delay.- 4.4. Wire Delay Model Integration.- 4.5. Summary.-
5.
Delphi: The Development of Libraries of Physical Models of Electronic
Components for an Integrated Design Environment.- 5.1. Background.- 5.2. The
DELPHI Project.- 5.3. Preliminary Investigations of compact models for
Mono-Chip Packages.- 5.4. A Compact Model of a 208-Lead PQFP Package.- 5.5.
Concluding Remarks.-
6. VHDL Floating Point Operations.- 6.1. Introduction.-
6.2. Framework for VHDL Code.- 6.3. Operations.- 6.4. Validation and
Benchmarking.- 6.5. Package Usability.- 6.6. Conclusions.-
7. Symbolic Model
Checking with Past and Future Temporal Modalities: Fundamentals and
Algorithms.- 7.1. Introduction.- 7.2. Fundamentals.- 7.3. The Temporal
Logic.- 7.4. Algorithms of the Symbolic Model Checker.- 7.5. Application to
VHDL.- 7.6. Conclusion.-
8. Krypton: Portable, Non-Reversible Encryption for
VHDL.- 8.1. Introduction.- 8.2. VHDL Source-Source Encryption.- 8.3. LVS: A
Compilation Environment for VHDL-Based Applications.- 8.4. Running KRYPTON.-
8.5. Example.- 8.6. Conclusions and Perspectives.
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