Muutke küpsiste eelistusi

E-raamat: Modeling Nanowire and Double-Gate Junctionless Field-Effect Transistors

(École Polytechnique Fédérale de Lausanne), (École Polytechnique Fédérale de Lausanne)
  • Formaat: EPUB+DRM
  • Ilmumisaeg: 01-Mar-2018
  • Kirjastus: Cambridge University Press
  • Keel: eng
  • ISBN-13: 9781108581394
Teised raamatud teemal:
  • Formaat - EPUB+DRM
  • Hind: 159,31 €*
  • * hind on lõplik, st. muud allahindlused enam ei rakendu
  • Lisa ostukorvi
  • Lisa soovinimekirja
  • See e-raamat on mõeldud ainult isiklikuks kasutamiseks. E-raamatuid ei saa tagastada.
Modeling Nanowire and Double-Gate Junctionless Field-Effect TransistorsSuurem pilt
  • Formaat: EPUB+DRM
  • Ilmumisaeg: 01-Mar-2018
  • Kirjastus: Cambridge University Press
  • Keel: eng
  • ISBN-13: 9781108581394
Teised raamatud teemal:

DRM piirangud

  • Kopeerimine (copy/paste):

    ei ole lubatud

  • Printimine:

    ei ole lubatud

  • Kasutamine:

    Digitaalõiguste kaitse (DRM)
    Kirjastus on väljastanud selle e-raamatu krüpteeritud kujul, mis tähendab, et selle lugemiseks peate installeerima spetsiaalse tarkvara. Samuti peate looma endale  Adobe ID Rohkem infot siin. E-raamatut saab lugeda 1 kasutaja ning alla laadida kuni 6'de seadmesse (kõik autoriseeritud sama Adobe ID-ga).

    Vajalik tarkvara
    Mobiilsetes seadmetes (telefon või tahvelarvuti) lugemiseks peate installeerima selle tasuta rakenduse: PocketBook Reader (iOS / Android)

    PC või Mac seadmes lugemiseks peate installima Adobe Digital Editionsi (Seeon tasuta rakendus spetsiaalselt e-raamatute lugemiseks. Seda ei tohi segamini ajada Adober Reader'iga, mis tõenäoliselt on juba teie arvutisse installeeritud )

    Seda e-raamatut ei saa lugeda Amazon Kindle's. 

The first of its kind, this is a detailed introduction to this new and fast-developing field. It covers the design, modeling, and operation of junctionless field effect transistors (FETs), as well as advantages and limitations. It is Ideal for graduate students and researchers working in semiconductor nanotechnology.

The first book on the topic, this is a comprehensive introduction to the modeling and design of junctionless field effect transistors (FETs). Beginning with a discussion of the advantages and limitations of the technology, the authors also provide a thorough overview of published analytical models for double-gate and nanowire configurations, before offering a general introduction to the EPFL charge-based model of junctionless FETs. Important features are introduced gradually, including nanowire versus double-gate equivalence, technological design space, junctionless FET performances, short channel effects, transcapacitances, asymmetric operation, thermal noise, interface traps, and the junction FET. Additional features compatible with biosensor applications are also discussed. This is a valuable resource for students and researchers looking to understand more about this new and fast developing field.

Muu info

A detailed introduction to the design, modeling, and operation of junctionless field effect transistors (FETs), including advantages and limitations.
Foreword xi
Preface xiii
List of Abbreviations
xv
List of Symbols
xvii
1 Introduction
1(14)
1.1 The Birth of the Transistor
1(1)
1.2 The Metal-Oxide--Semiconductor Field-Effect Transistor
1(1)
1.3 Moore's Law, Limits of CMOS Scaling, and Alternative MOSFET Structures
2(2)
1.3.1 Scaling in Bulk MOSFETs
2(1)
1.3.2 Silicon-on-Insulator MOSFETs
3(1)
1.4 The Junctionless Concept
4(5)
1.4.1 Working Principle of Junctionless MOSFETs
4(2)
1.4.2 Diversity in Junctionless Architectures
6(3)
1.5 Short-Channel Effects in Junctionless FETs
9(1)
1.6 Mobility in Junctionless FETs
10(1)
1.7 The Critical Aspect of Random Dopant Fluctuation
11(3)
1.7.1 Random Dopant Fluctuations in Junctionless FETs
12(2)
1.8 Summary
14(1)
2 Review on Modeling Junctionless FETs
15(14)
2.1 Modeling Junctionless Double-Gate MOSFETs
15(10)
2.1.1 Full Depletion Approximation
15(2)
2.1.2 Enhanced Depletion Approximation
17(1)
2.1.3 Surface Potential-based Approach
17(2)
2.1.4 Simplified Current Model Involving Pinch-Off
19(1)
2.1.5 Semiempirical Charge-based Approach
20(1)
2.1.6 Analytical Approach based on Conventional Inversion-Mode MOSFETs
20(1)
2.1.7 Parabolic Approximation and Full-Range Drain Current
20(1)
2.1.8 Gaussian Distribution of Mobile Charge Density
21(1)
2.1.9 Simple Model to Estimate Junctionless FET Performances
22(1)
2.1.10 Explicit Drain Current Model Relying on Charge-based Approach
23(1)
2.1.11 Modeling of Quantum Mechanical Effects
23(1)
2.1.12 Short-Channel Effects in Subthreshold
24(1)
2.1.13 Transcapacitance Modeling
25(1)
2.1.14 Modeling Asymmetry in Junctionless Double-Gate MOSFETs
25(1)
2.2 Modeling Junctionless Nanowire MOSFETs
25(3)
2.2.1 Short-Channel Effects in the Subthreshold
27(1)
2.2.2 Transcapacitance Modeling in Junctionless Nanowire FETs
27(1)
2.2.3 Quantum Mechanical Effects in Junctionless Nanowire FETs
28(1)
2.3 Summary
28(1)
3 The EPFL Charge-based Model of Junctionless Field-Effect Transistors
29(31)
3.1 Charge-based Modeling of Junctionless Double-Gate Field-Effect Transistors
29(21)
3.1.1 Recalling Basics of Semiconductor Statistics
29(3)
3.1.2 Approximate Solution of the Poisson--Boltzmann Equation in Junctionless Double-Gate MOSFET
32(3)
3.1.3 Introduction of Symmetric Gate Capacitances
35(1)
3.1.4 Derivation of Explicit Voltage--Charge Relationships
36(2)
3.1.5 Analytical versus Numerical Simulations
38(3)
3.1.6 Threshold Voltage in Junctionless FETs
41(1)
3.1.7 Derivation of the Channel Current
41(3)
3.1.8 Evaluation of the Charge Integral
44(1)
3.1.9 General Treatment of the Current in Junctionless Double-Gate MOSFETs
45(1)
3.1.10 Simulation Results
46(4)
3.2 A Common Core Model for Junctionless Nanowires and Symmetric DG FETs
50(5)
3.2.1 Analysis of Electrostatics in Junctionless Nanowire FETs
50(3)
3.2.2 Derivation of the Current in a Junctionless Nanowire
53(1)
3.2.3 Simulations
53(2)
3.3 Explicit Model for Long-Channel Gate-All-Around Junctionless MOSFETs
55(3)
3.3.1 Approximated Solution in Depletion
57(1)
3.3.2 Approximated Solution in Accumulation Mode
58(1)
3.3.3 Approximated Solution in Weak Accumulation Mode
58(1)
3.4 Summary
58(2)
4 Model-Driven Design-Space of Junctionless FETs
60(16)
4.1 Off-Current and Inversion Layer in Junctionless FETs
60(1)
4.2 Electrostatics in Junctionless Double-Gate MOSFET including Minority Carriers
61(14)
4.2.1 Role of the Channel Potential
64(1)
4.2.2 Estimation of the Critical Potentials
65(4)
4.2.3 Minimum Mobile Charge Density
69(1)
4.2.4 Estimation of On/Off-Current Ratio in Long-Channel Junctionless FETs
69(4)
4.2.5 Rail-to-Rail Supply Voltage Benchmark
73(2)
4.3 Summary
75(1)
5 Generalization of the Charge-based Model: Accounting for Inversion Layers
76(10)
5.1 Electrostatics including Minority Carriers
76(6)
5.1.1 Coexistence of Depletion and Inversion: General Treatment
78(2)
5.1.2 Charge--Voltage Relationships
80(1)
5.1.3 Inversion Layer-Induced Capacitance in Junctionless Double-Gate MOSFET
81(1)
5.2 Simulations and Model Assessments
82(3)
5.2.1 Impact of Hole Layer on Drain Current
83(2)
5.3 Summary
85(1)
6 Predicted Performances of Junctionless FETs
86(6)
6.1 Device Scaling Principle
86(2)
6.2 Considerations on Intrinsic-Delay Scaling
88(3)
6.3 Summary
91(1)
7 Short-Channel Effects in Symmetric Junctionless Double-Gate FETs
92(16)
7.1 Electrostatics in Short-Channel Junctionless DG MOSFETS in the Subthreshold
92(6)
7.1.1 Approximate Solution of the Potential Distribution
93(1)
7.1.2 Assessment of the Center Potential with Regard to Numerical Simulations
94(4)
7.2 Subthreshold Current, Subthreshold Swing, and DIBL
98(9)
7.2.1 The Minimum Potential
98(2)
7.2.2 Channel Current in Subthreshold
100(3)
7.2.3 Subthreshold Swing in Junctionless FETs
103(1)
7.2.4 DIBL in Junctionless FETs
104(3)
7.3 Summary
107(1)
8 Modeling AC Operation in Symmetric Double-Gate and Nanowire JL FETs
108(31)
8.1 Transcapacitance Matrix in Symmetric Double-Gate FETs
108(2)
8.2 General Case
110(6)
8.2.1 Expressing dy versus dVch
111(1)
8.2.2 Expressing Qm(y)dVch
112(1)
8.2.3 Expressing y/LG versus Qm(y)
112(4)
8.3 Special Case of a Channel Uniformly Depleted/Accumulated
116(3)
8.3.1 Channel in Depletion Mode
116(2)
8.3.2 Channel in Accumulation Mode
118(1)
8.4 Analytical Expressions for the Local Charge Derivatives
119(2)
8.5 Simulations and Discussion
121(3)
8.6 Cubic Approximation of Qm(y) and Transcapacitances
124(6)
8.6.1 Hybrid Channel
124(2)
8.6.2 Uniform Channels
126(1)
8.6.3 Evaluation of Flat-Band Position along the Hybrid Channel
127(1)
8.6.4 Evaluation of the Transcapacitances
127(3)
8.7 Transcapacitances in Gate-All-Around Junctionless Nanowire FETs
130(2)
8.7.1 Equivalent Parameters Definition
130(1)
8.7.2 Simulations
131(1)
8.8 A Simplified Approach to Transcapacitance Modeling in Junctionless Nanowire FETs
132(6)
8.8.1 Channel in Depletion Mode
133(2)
8.8.2 Channel in Accumulation Mode
135(3)
8.9 Summary
138(1)
9 Modeling Asymmetric Operation of Double-Gate Junctionless FETs
139(16)
9.1 General Considerations in Asymmetric Junctionless Double-Gate FETs
139(3)
9.2 Analysis Restricted to Depletion or Accumulation
142(6)
9.2.1 Potential Extremum Inside the Channel
142(3)
9.2.2 Extremum Potential Outside the Channel
145(1)
9.2.3 The Iterative Solution
146(1)
9.2.4 Simulations
146(2)
9.3 Coexistence of Depletion and Accumulation
148(2)
9.3.1 Modeling Depleted--Accumulated Channels
148(1)
9.3.2 Simplifying Assumptions
149(1)
9.3.3 Assessment of Continuity at the Transition Coordinates
149(1)
9.4 Derivation of the Current
150(1)
9.5 Simulations
151(2)
9.5.1 Potential Induced Asymmetry
151(1)
9.5.2 Structural Asymmetry
151(1)
9.5.3 Approximate Expression for the Current
151(2)
9.5.4 Limitations
153(1)
9.6 Summary
153(2)
10 Modeling Noise Behavior in Junctionless FETs
155(9)
10.1 Thermal-Noise Modeling
155(4)
10.2 Induced Gate Noise in Junctionless FET
159(2)
10.3 Cross-Correlation Noise in Junctionless FETs
161(2)
10.4 Summary
163(1)
11 Carrier Mobility Extraction Methodology in JL and Inversion-Mode FETs
164(10)
11.1 Y Function and Mobility Extraction in Junctionless FETs
164(2)
11.2 Model-Independent Mobility-Extraction Method in Junctionless FETs
166(5)
11.2.1 General Treatment
166(3)
11.2.2 Mobility Extraction in Double-Gate Junctionless FETs
169(1)
11.2.3 A Simplified Approach
170(1)
11.3 Extending the Method to Inversion-Mode FETs
171(1)
11.4 Limitations
172(1)
11.5 Summary
173(1)
12 Revisiting the Junction FET: A Junctionless FET with an ∞ Gate Capacitance
174(9)
12.1 Principle Operation of the JFET
174(1)
12.2 Charge-based Modeling of Double-Gate JFETs
175(2)
12.2.1 Charge--Voltage and Pinch-Off Voltage in Double-Gate JFETs
175(1)
12.2.2 Channel Current in Double-Gate JFETs
176(1)
12.2.3 Simulations
177(1)
12.3 Modeling Small Signals in JFETs
177(5)
12.3.1 Transconductance
177(2)
12.3.2 Transcapacitances in JFET
179(2)
12.3.3 Simulations
181(1)
12.4 Summary
182(1)
13 Modeling Junctionless FET with Interface Traps Targeting Biosensor Applications
183(14)
13.1 Principle of Semiconductor-based Field-Effect Biosensors
183(2)
13.2 Modeling Surface Traps in Junctionless FETs
185(12)
13.2.1 General Considerations for Interface Traps
185(1)
13.2.2 Modeling Trapped Charges at the Semiconductor/Insulator Interface in Junctionless FETs
186(6)
13.2.3 Current Derivation
192(1)
13.2.4 The Case of Continuous Energy-Trap Distribution
193(2)
13.2.5 Summary
195(2)
Appendix A Design-Space of Twin-Gate Junctionless Vertical Slit FETs
197(3)
A.1 Design-Space of Twin-Gate Junctionless Vertical Slit FETs
197(3)
A.1.1 Device Structure
197(1)
A.1.2 Electrostatics in Junctionless VeSFET and Design-Space
197(3)
Appendix B Transient Off-Current in Junctionless FETs
200(3)
Appendix C Derivatives of Mobile Charge Density with Respect to VGS and VDS
203(1)
Appendix D Global Charge Density at Drain in Depletion Mode
204(2)
Appendix E Global Charge Density at Drain in Accumulation Mode
206(2)
Appendix F The EPFL Junctionless MODEL
208(7)
F.1 The EPFL-Junctionless Model Modules
208(1)
F.2 Source Code Modules and Library
209(1)
F.3 DC Implementation in Junctionless FETs
210(1)
F.4 AC Implementation in Junctionless FETs
211(2)
F.5 Junctionless Double-Gate and Nanowire FET Amplifier
213(1)
F.6 Junctionless Double-Gate and Nanowire FET Inverter
214(1)
References 215(16)
Index 231
Farzan Jazaeri is a Scientist at the Ecole Polytechnique Fédérale de Lausanne where his research interests focus on semiconductor devices and physics, and particularly the modeling and fabrication of field-effect transistors. Jean-Michel Sallese is a Senior Scientist at the Ecole Polytechnique Fédérale de Lausanne. He specialises in the analytical modeling of bulk and multigate field-effect transistors.
Lisainfo e-raamatute kohta Lisainfo e-raamatute kohta
Püsilink: https://www.kriso.ee/db/97811085813946e.html
Märksõnad: